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LMX2541SQX2380E Datasheet(PDF) 10 Page - Texas Instruments |
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LMX2541SQX2380E Datasheet(HTML) 10 Page - Texas Instruments |
10 / 64 page tCES tCS D19 D18 D17 D16 tCH tCWH tCWL D15 D0 C3 C2 C1 C0 MSB LSB DATA CLK LE tES tEWH LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.) Symbol Parameter Conditions Min Typ Max Units 10 kHz Offset -83.9 100 kHz Offset -108.3 fRFout = Min VCO 1 MHz Offset -129.9 Frequency 10 MHz offset -150.6 20 MHz Offset -156.5 Phase Noise L(f)Fout dBc/Hz 3740E 10 kHz Offset -81.6 100 kHz Offset -106.5 fRFout = Max VCO 1 MHz Offset -127.7 Frequency 10 MHz Offset -148.6 20 MHz Offset -154.2 Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN) VIH High-Level Input Voltage 1.6 Vcc V VIL Low-Level Input Voltage 0.4 V IIH High-Level Input Current VIH = 1.75, XO = 0 -5 5 µA IIL Low-Level Input Current VIL = 0 V , XO = 0 -5 5 µA VOH High-Level Output Voltage IOH = 500 µA 2.0 V VOL Low-Level Output Voltage IOL = -500 µA 0.0 0.4 V ILeak Leakage Current Ftest/LD and FLout Pins Only -5 5 µA MICROWIRE Timing tCE Clock to Enable Low Time See Data Input Timing 25 ns tCS Data to Clock Set Up Time See Data Input Timing 25 ns tCH Data to Clock Hold Time See Data Input Timing 20 ns tCWH Clock Pulse Width High See Data Input Timing 25 ns tCWL Clock Pulse Width Low See Data Input Timing 25 ns tCES Enable to Clock Set Up Time See Data Input Timing 25 ns tEWH Enable Pulse Width High See Data Input Timing 25 ns Serial Data Timing Diagram There are several other considerations for programming: • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. • A slew rate of at least 30 V/ μs is recommended for the CLK, DATA, and LE signals. • After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state. • When using the part in Full Chip Mode with the Integrated VCO, LE should be kept high no more than 1 us after the programming of the R0 register. Failure to do so may interfere with the digital VCO calibration. • If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming. 10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E LMX2541SQ3320E LMX2541SQ3740E |
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