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RFFC5071/5072

Proposed

Prelim DS101020

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

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Note 1: An RC low-pass filter could be used on this line to reduce digital noise.

Note 2: If the device is under software control this input can be configured as a general purpose output (GPO).

Note 3: Connect a 51K

 resistor from this pin to ground. This pin is sensitive to low frequency noise injection.

Note 4: DC voltage should not be applied to this pin. Use either an AC coupling capacitor as part of lumped element matching

network or a transformer (see evaluation board schematic).

Note 5: This pin must be connected to ANA_VDD2 using an RF choke or center-tapped transformer (see evaluation board

schematic).

Pin

Function

Description

1

2

EXT_LO

External local oscillator input.

3

4

REXT

External bandgap bias resistor. See note 3.

5

ANA_VDD1

Analog supply. Use good RF decoupling.

6

LFILT1

Phase detector output. Low-frequency noise-sensitive node.

7

LFILT2

Loop filter op-amp output. Low-frequency noise-sensitive node.

8

LFILT3

VCO control input. Low-frequency noise-sensitive node.

9

10

REF_IN

Reference input. Use AC coupling capacitor.

11

NC

12

TM

Connect to ground.

13

MIX1_IPN

Differential input 1 (see note 4). On RFFC5072 this pin is NC.

14

MIX1_IPP

Differential input 1 (see note 4). On RFFC5072 this pin is NC.

15

16

17

MIX1_OPN

Differential output 1 (see note 5). On RFFC5072 this pin is NC.

18

MIX1_OPP

Differential output 1 (see note 5). On RFFC5072 this pin is NC.

19

DIG_VDD

Digital supply. Should be decoupled as close to the pin as possible.

20

NC

21

NC

22

ANA_VDD2

Analog supply. Use good RF decoupling.

23

MIX2_IPP

Differential input 2 (see note 4).

24

MIX2_IPN

Differential input 2 (see note 4).

25

GPO3/FM

General purpose output / frequency control input.

26

27

MIX2_OPN

Differential output 2 (see note 5).

28

MIX2_OPP

Differential output 2 (see note 5).

29

RESETX

Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.

30

ENX

Serial interface select (active low). See note 1.

31

SCLK

Serial interface clock. See note 1.

32

SDATA

Serial interface data. See note 1.

Exposed paddle

Ground reference, should be connected to PCB ground through a low impedance path.