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NM24C17UFLZMT8 Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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NM24C17UFLZMT8 Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 13 page 8 www.fairchildsemi.com NM24C16U/17U Rev. B.1 DS800010-10 SDA SCL STOP CONDITION START CONDITION WORD n 8th BIT ACK tWR Write Cycle Timing (Figure 1) Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. Data Validity (Figure 2) Start and Stop Definition (Figure 3) Acknowledge Response from Receiver (Figure 4) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 18 9 START ACKNOWLEDGE SDA SCL START CONDITION STOP CONDITION SCL DATA STABLE DATA CHANGE SDA DS800010-11 DS800010-12 DS800010-13 |
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