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PCM1750U Datasheet(PDF) 9 Page - Texas Instruments |
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PCM1750U Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 21 page  9 ® PCM1750 the next rising edge of CLKIN, at the end of the test interval, the comparator latch is strobed, providing a feedback logic level which tells the second data latch if bit-2 should be kept or rejected. This logic level is stored in the data latch and is passed on to switch S2 via the NOR gate on the falling edge of the pulse from SR2. This decision to keep or reject bit-2 moves the comparator input closer to a null condition, namely, zero potential. This sequential process continues for bit-3 through bit-18 and nulls the comparator inputs to within a value limited by the total system noise and the resolution/speed of the comparator. Notice from the timing diagram in Figure 2 that the succes- sive approximation algorithm operates synchronously with an external clock to minimize digitally-coupled switching noise from corrupting either the sample-to-hold operation or the critical comparator bit decisions. The two serial output data streams are derived synchronously from the respective latched comparator outputs and are available after a delay of one CLKIN cycle as illustrated in Figure 2. The serial output driver cells are TTL and CMOS compatible. DIFFERENTIAL LINEARITY CALIBRATION To understand the calibration of the PCM1750 it is neces- sary to discuss some of the characteristics of poly-poly capacitors. Poly capacitors are known to have equal or better stability and matching properties when compared to other precision components such as thin film resistors. On a well controlled process, ratio matching is typically 0.1% — a very respectable number for an untrimmed component. Even more impressive is their ratio tracking versus temperature of approximately 0.1ppm/ °C. Achieving DLE (differential linearity error) of less than 1/2 LSB at the 16-bit level requires ratio matching of the more significant bits to about 0.001%. Since the untrimmed ratio matching of poly capacitors is about two orders of magni- tude larger than this requirement, a one-time factory calibra- tion of the upper bits is required as described in the next section. Next, consider the effect of temperature due to the ratio tracking of 0.lppm/ °C. Over a 50°C span, DLE will change less than 1LSB at 18-bits; therefore, recalibration at temperature extremes is not necessary. Because of this excellent stability versus temperature (and versus time, also), the one-time factory calibration to correct initial DLE is more than satisfactory in meeting the accuracy requirements of the PCM1750. TDAC OPERATION Operation of the TDAC (trim DAC), which is laser trimmed at the wafer level, is described using bit-1 as an example. Switch S1T (see Figure 1) operates between two voltage levels—a reference level set by voltage divider Ra, Rb and a laser trimmable level set by R1a, R1b. The differences of these two levels is coupled by capacitor C1T to the minus input of the comparator to generate a correction voltage for DQ LR DQ R SR 2 DQ L R DQ L R DQ R SR 18 DQ L R DQ L R DQ S SR 1 DQ L R DQ R SR 19 Control Logic To MSB Switches Left To Bit 2 Switches Left To Bit 18 Switches Left To MSB Switches Right To Bit 2 Switches Right To Bit 18 Switches Right Serial Data From Latching Comparator Serial Data From Latching Comparator Data Latches Left Channel 19-Bit Shift Register Data Latches Right Channel FIGURE 4. PCM1750 Successive Approximation Logic Diagram. |
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Similar Description - PCM1750U |
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