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SN65LVDT100DGK Datasheet(PDF) 1 Page - Texas Instruments |
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SN65LVDT100DGK Datasheet(HTML) 1 Page - Texas Instruments |
1 / 25 page www.ti.com FEATURES DESCRIPTION APPLICATIONS FUNCTIONAL DIAGRAM 8 2 3 4 7 6 VCC A B VBB Y Z 2 Gbps 223 - 1 PRBS VCC = 3.3 V VID = 200 mV VIC = 1.2 V Horizontal Scale= 200 ps/div Vert.Scale= 200 mV/div EYE PATTERN 1 GHz SN65LVDS100 and SN65LVDS101 2 3 7 6 A B Y Z 110 Ω SN65LVDT100 and SN65LVDT101 SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 DIFFERENTIAL TRANSLATOR/REPEATER • Designed for Signaling Rates (1) ≥ 2 Gbps The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are a high-speed differential re- • Total Jitter < 65 ps ceiver and driver connected as a repeater. The • Low-Power Alternative for the MC100EP16 receiver accepts low-voltage differential signaling • Low 100 ps (Max) Part-To-Part Skew (LVDS), positive-emitter-coupled logic (PECL), or cur- • 25 mV of Receiver Input Threshold Hysteresis rent-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL Over 0-V to 4-V Common-Mode Range output signal. The signal path through the device is • Inputs Electrically Compatible With LVPECL, differential for low radiated emissions and minimal CML, and LVDS Signal Levels added jitter. • 3.3-V Supply Operation The outputs of the SN65LVDS100 and • LVDT Integrates 110- Ω Terminating Resistor SN65LVDT100 are LVDS levels as defined by • Offered in SOIC and MSOP TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100- Ω characteristic impedance. • 622 MHz Central Office Clock Distribution • High-Speed Network Routing The SN65LVDT100 and SN65LVDT101 include a 110- Ω differential line termination resistor for less • Wireless Basestations board space, fewer components, and the shortest • Low Jitter Clock Repeater stub length possible. They do not include the VBB • Serdes LVPECL Output to FPGA LVDS voltage reference found in the SN65LVDS100 and Input Translator SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When not used, VBB should be unconnected or open. (1) The signaling rate of a line is the number of voltage All devices are characterized for operation from transitions that are made per second expressed in the units bps (bits per second). –40 °C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRO- Copyright © 2002–2004, Texas Instruments Incorporated DUCTION DATA information current as of publication date. Prod- ucts conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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