SN75LBC179, SN65LBC179, SN65LBC179Q

LOW POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS

SLLS173F − JANUARY 1994 − REVISED APRIL 2006

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VOD

Vtest

R1

375

Ω

0 V or 3 V

Z

D

R2

375

Ω

Vtest

Y

RL = 60 Ω

− 7 V < Vtest < 12 V

Figure 2. Differential Output Voltage Test Circuit

0 V

3 V

tt(OD)

tt(OD)

1.5 V

td(ODH)

50%

Output

Input

TEST CIRCUIT

VOLTAGE WAVEFORMS

td(ODL)

RL = 54 Ω

Output

Generator

(see Note A)

50

Ω

1.5 V

50%

CL = 50 pF

(see Note B)

1.5 V

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR

≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO =50 Ω.

B. CL includes probe and jig capacitance.

Figure 3. Driver Test Circuits and Differential Output Delay and Transition Time Voltage Waveforms

TEST CIRCUIT

VOLTAGE WAVEFORMS

VOL

VOH

3 V

0 V

tPHL

tPLH

Output

Input

1.3 V

1.5 V

1.3 V

50

Ω

Output

1.5 V

Generator

(see Note A)

A

B

tt

90%

10%

10%

90%

tt

CL = 15 pF

(see Note B)

1.5 V

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR

≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO =50 Ω.

B. CL includes probe and jig capacitance.

Figure 4. Receiver Test Circuit and Propagation Delay and Transition Time Voltage Waveforms