LM2642

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SNVS203I – MAY 2002 – REVISED APRIL 2013

system.

ON/SS1 (Pin 9) Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling

this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled

below 1.2V, the whole chip goes into shut down mode. Adding a capacitor to this pin provides a soft-start

feature that minimizes inrush current and output voltage overshoot.

ON/SS2 (Pin 10) Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for

simultaneous startup or for parallel operation.

FB2 (Pin 11) Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2

output voltage.

COMP2 (Pin 12) Compensation pin for Channel 2. This is the output of the internal transconductance amplifier.

The compensation network should be connected between this pin and the signal ground SGND (Pin 8).

ILIM2 (Pin 13) Current limit threshold setting for Channel 2. See ILIM1 (Pin 2).

KS2 (Pin 14) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2. See KS1 (Pin 1).

RSNS2 (Pin 15) The negative (-) Kelvin sense for the internal current sense amplifier of Channel 2. Connect this

pin to the low side of the current sense resistor that is placed between VIN and the drain of the top

MOSFET. When the Rds of the top MOSFET is used for current sensing, connect this pin to the source of

the top MOSFET. Always use a separate trace to form a Kelvin connection to this pin.

SW2 (Pin 16) Switch-node connection for Channel 2, which is connected to the source of the top MOSFET of

Channel 2. It serves as the negative supply rail for the top-side gate driver, HDRV2.

HDRV2 (Pin 17) Top-side gate-drive output for Channel 2. HDRV is a floating drive output that rides on the

corresponding switching-node voltage.

CBOOT2 (Pin 18) Bootstrap capacitor connection. It serves as the positive supply rail for the Channel 2 top-side

gate drive. Connect this pin to VDD2 (Pin 19) through a diode, and connect the low side of the bootstrap

capacitor to SW2 (Pin16).

VDD2 (Pin 19) The supply rail for the Channel 2 low-side gate drive. Connected to VLIN5 (Pin 7) through a 4.7

Ω

resistor and bypassed to power ground with a ceramic capacitor of at least 1µF. Tie this pin to VDD1 (Pin

24).

LDRV2 (Pin 20) Low-side gate-drive output for Channel 2.

PGND (Pin 21) The power ground connection for both channels. Connect to the ground rail of the system.

VIN (Pin 22) The power input pin for the chip. Connect to the positive (+) input rail of the system. This pin must

be connected to the same voltage rail as the top FET drain (or the current sense resistor when used).

LDRV1 (Pin 23) Low-side gate-drive output for Channel 1.

VDD1 (Pin 24) The supply rail for Channel 1 low-side gate drive. Tie this pin to VDD2 (Pin 19).

CBOOT1 (Pin 25) Bootstrap capacitor connection. It serves as the positive supply rail for Channel 1 top-side gate

drive. See CBOOT2 (Pin 18).

HDRV1 (Pin 26) Top-side gate-drive output for Channel 1. See HDRV2 (Pin 17).

SW1 (Pin 27) Switch-node connection for Channel 1. See SW2 (Pin16).

RSNS1 (Pin 28) The negative (-) Kelvin sense for the internal current sense amplifier of Channel 1. See RSNS2

(Pin 15).

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