bq2019

ADVANCED BATTERY MONITOR IC

SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003

11

POST OFFICE BOX 655303

APPLICATION INFORMATION

register interface (continued)

Table 4. bq2019 Registers

HDQ

ADDRESS

NAME

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0x78–0x7F

IDROM

8 bytes of factory-programmed ROM

0x77

CAL/OFFCTH

COMPEN

CALREQ

CALOK

CHGOFF

Flash-shadowed VFC offset bits 19–16

0x76

OFFCTM

Flash-shadowed offset register bits 15–8

0x75

OFFCTL

Flash-shadowed offset register bits 7–0

0x74

—

Reserved

0x73

—

Reserved

0x72

—

Reserved

0x71

Reserved

0x70

FPA

Program address byte

0x6F

FPD

Flash program data byte

0x6E

DCRH

Discharge count register high byte

0x6D

DCRL

Discharge count register low byte

0x6C

CCRH

Charge count register high byte

0x6B

CCRL

Charge count register low byte

0x6A

SCRH

Self-discharge count register high byte

0x69

SCRL

Self-discharge count register low byte

0x68

DTCH

Discharge timer counter register high byte

0x67

DTCL

Discharge timer count register low byte

0x66

CTCH

Charge timer counter register high byte

0x65

CTCL

Charge timer counter register low byte

0x64

MODE/WOE

TVOS

DISREG

STC

STD

WOE2

WOE1

WOE0

BIT0

0x63

CLR

RSVD

POR

STAT

CTC

DTC

SCR

CCR

DCR

0x62

FCMD

Flash/control command register

0x61

TMPH

Reserved

TEMP[8]

0x60

TMPL

TEMP[7:0]

0x40–0x5F

Flash

PAGE2, 32 bytes of flash

0x20–0x3F

Flash

PAGE1, 32 bytes of flash

0x00–0x1F

RAM/flash

PAGE0, 32 bytes of flash-shadowed RAM

memory

ID ROM

The bq2019 has 8 bytes of ID ROM. This data field can be factory programmed to the customer request, insuring

a unique and secure product serialization. Contact your Texas Instruments representative for details.

flash-shadowed RAM

The host system has direct access to read and modify 32 bytes of RAM. These 32 bytes are shadowed by 32

bytes of flash to provide nonvolatile storage of battery conditions. The information stored in RAM is transferred

to flash, and the information stored in flash is transferred to RAM by writing a single command into the flash

command register (FCMD). When a power-on-reset occurs, PAGE0 of flash and three flash-shadowed offset

bytes are transferred to RAM. (The host is responsible for storing offset value in flash.) For more details, refer

to the flash command register section.