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BQ2019 Datasheet(PDF) 20 Page - Texas Instruments

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Part No. BQ2019
Description  ADVANCED BATTERY MONITORIC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

BQ2019 Datasheet(HTML) 20 Page - Texas Instruments

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bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
register descriptions (continued)
flash command register (FCMD)
The FCMD register (address 0x62) is the flash command register that programs a single flash byte-location,
performs flash page erase, transfers RAM to flash and flash to RAM, enters sleep mode, and calibrates the VFC
and power-down. These functions are performed by writing the desired command code to the FCMD register.
After the bq2019 has finished executing the issued command, the flash command register is cleared.
0x0F
Program byte command code. This code ANDs the contents of the FPD register with the
contents of flash byte location pointed to by the contents of the FPA register.
0x40
Erase page 0 command code. This code erases all the bytes of flash from address 0x00 to
0x1F.
0x41
Erase page 1 command code. This code erases all the bytes of flash from address 0x20 to
0x3F.
0x42
Erase page 2 command code. This code erases all the bytes of flash from address 0x40 to
0x5F.
0x43
Erase offset control register shadow flash. This code erases the 3 bytes of flash that
shadow the Offset Control Register located at HDQ address 0x75–0x77.
0x45
RAM-to-flash transfer code. This code programs the contents of the RAM into Page 0 flash,
addresses 0x00 though 0x1F.
0x48
flash to RAM transfer code. This code copies the contents of the Page 0 flash into RAM.
0xF6
Power-Down code. This code places the bq2019 into the sleep mode when the conditions
are met as indicated by the WOE bits in the MODE/WOE register. The part remains in sleep
mode until a high-to-low or low-to-high transition occurs on the HDQ pin.
0xF7
Calibrate VFC and power-down code. This command code will initiate a calibration once
VSR drops below Vwoe. If the HDQ line toggles low to high to high to low before calibration
completes, the device will NOT enter the low power mode. Sending this code must be the
last HDQ communication if the device is to go into SLEEP mode.
temperature registers (TMPH, TMPL)
The TMPH (address 0x61) and the TMPL registers (address 0x60) reports die temperature in hex format in units
of
°K, with an accuracy of typically ±3°K. The temperature is reported as 9 bits of data, using all 8 bits of the
TMPL register and LSB of the TMPH register. The temperature should be read as the concatenation of TMPH[0]
and TMPL[7:0].
The 7 MSBs of TMPH, TMPH[7:1], are cleared on POR. The bits are reserved and should be written to 0 if the
host attempts to write to the TMPH register. The 7 bits should also be masked off when reading the temperature
to ensure that incorrect data is not used when calculating the temperature.


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