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PIC18F66J50 Datasheet(PDF) 2 Page - Microchip Technology |
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PIC18F66J50 Datasheet(HTML) 2 Page - Microchip Technology |
2 / 16 page PIC18F87J50 FAMILY DS80481A-page 2 © 2009 Microchip Technology Inc. TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A2 A3 A4 MSSP I2C™ Slave 1. With I2C slave reception, need to read data promptly XX X MSSP I2C Master 2. With I2C Master mode, narrow clock width upon slave clock stretch XX X EUSART Interrupts 3. If interrupts are enabled, 2 TCY delay needed after re-enabling the module XX X MSSP SPI Master mode 4. SPI master, write collision for FOSC/64 and Timer2/2 XX X PORTH RH0, RH1 5. In certain cases, PMP can override RH0 and RH1 XX X Note 1: Only those issues indicated in the last column apply to the current silicon revision. |
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