ADV7194 datasheet(36/69 Pages) AD

Part #	ADV7194

Description	Professional Extended-10 Video Encoder with 54 MHz Oversampling

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ADV7194

–36–

REV. A

Chroma Delay Control (MR95–MR97)

The Chroma signal can be delayed by up to eight clock cycles

at 27 MHz using MR94–95. For further information see also

the Chroma/Luma Delay section.

TIMING REGISTER 0 (TR07–TR00)

(Address (SR4–SR0) = 0AH)

Figure 66 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to.

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

This bit controls whether the ADV7194 is in master or slave mode.

Timing Mode Selection (TR01–TR02)

These bits control the timing mode of the ADV7194. These

modes are described in more detail in the Timing and Con-

trol section of the data sheet.

BLANK Input Control (TR03)

This bit controls whether the

BLANK input is used to accept

blank signals or whether blank signals are internally generated.

Note: When this input pin is tied high (to 5 V), the input is dis-

abled regardless of the register setting. It, therefore, should be

tied low (to Ground) to allow control over the I

2C register.

Luma Delay (TR04–TR05)

The luma signal can be delayed by up to 222 ns (or six clock

cycles at 27 MHz) using TR04–05. For further information see

Chroma/Luma Delay section.

Min Luminance Value (TR06)

This bit is used to control the minimum luma output value

by the ADV7194. When this bit is set to a Logic 1, the luma is

limited to 7IRE below the blank level. When this bit is set to (0),

the luma value can be as low as the sync bottom level.

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the inter-

nal timing counters. This bit should be toggled after power-up,

reset or changing to a new timing mode.

TIMING REGISTER 1

(TR17–TR10)

(Address (SR4–SR0) = 0BH)

Timing Register 1 is an 8-bit-wide register.

Figure 67 shows the various operations under the control of

Timing Register 1. This register can be read from as well written

to. This register can be used to adjust the width and position of

the master mode timing signals.

TR1 BIT DESCRIPTION

HSYNC Width (TR10–TR11)

These bits adjust the

HSYNC pulsewidth.

TPCLK = one clock cycle at 27 MHz.

HSYNC to VSYNC Delay Control (TR13–TR12)

These bits adjust the position of the

HSYNC output relative to

the VSYNC output.

TPCLK = one clock cycle at 27 MHz.

HSYNC to VSYNC Rising Edge Control (TR14–TR15)

When the ADV7194 is in Timing Mode 1, these bits adjust the

position of the

HSYNC output relative to the VSYNC output ris-

ing edge.

TPCLK = one clock cycle at 27 MHz.

VSYNC Width (TR14–TR15)

When the ADV7194 is conﬁgured in Timing Mode 2, these bits

adjust the

VSYNC pulsewidth.

TPCLK = one clock cycle at 27 MHz.

HSYNC to Pixel Data Adjust (TR16–TR17)

This enables the

HSYNC to be adjusted with respect to the

pixel data. This allows the Cr and Cb components to be swapped.

This adjustment is available in both master and slave timing

modes.

TPCLK = one clock cycle at 27 MHz.

MR97

MR96

MR95

MR94

MR93

MR92

MR91

MR90

ZERO MUST

BE WRITTEN

TO THESE BITS

MR97 MR96

CHROMA

DELAY CONTROL

MR95 MR94

0

0ns DELAY

0

1

148ns DELAY

1

0

296ns DELAY

1

RESERVED

UNDERSHOOT

LIMITER

MR91 MR90

0

DISABLED

01

–11 IRE

10

–6 IRE

11

–1.5 IRE

0

DISABLE

1

ENABLE

MR93

BLACK BURST

LUMA DAC

0

DISABLE

1

ENABLE

MR92

BLACK BURST

Y-DAC

Figure 65. Mode Register 9, MR9

TR07

TR06

TR05

TR04

TR03

TR02

TR01

TR00

0

LUMA MIN =

SYNC BOTTOM

1

LUMA MIN =

BLANK –7.5 IRE

TR06

MIN LUMINANCE VALUE

0

ENABLE

1

DISABLE

TR03

BLANK INPUT

CONTROL

TIMING

REGISTER RESET

TR07

0

SLAVE TIMING

1

MASTER TIMING

TR00

MASTER / SLAVE

CONTROL

LUMA DELAY

TR05 TR04

0

0ns DELAY

0

1

74ns DELAY

1

0

148ns DELAY

1

222ns DELAY

TR02 TR01

0

MODE 0

0

1

MODE 1

1

0

MODE 2

1

MODE 3

TIMING MODE

SELECTION

Figure 66. Timing Register 0

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