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AD652JP-REEL7 Datasheet(PDF) 6 Page - Analog Devices |
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AD652JP-REEL7 Datasheet(HTML) 6 Page - Analog Devices |
6 / 28 page AD652 Rev. C | Page 6 of 28 THEORY OF OPERATION A synchronous VFC is similar to other voltage-to-frequency converters in that an integrator is used to perform a charge- balance of the input signal with an internal reference current. However, rather than using a one-shot as the primary timing element, which requires a high quality and low drift capacitor, a synchronous voltage-to-frequency converter (SVFC) uses an external clock. This allows the designer to determine the system stability and drift based upon the external clock selected. A crystal oscillator may also be used if desired. The SVFC architecture provides other system advantages besides low drift. If the output frequency is measured by counting pulses gated to a signal that is derived from the clock, the clock stability is unimportant and the device simply performs as a voltage-controlled frequency divider, producing a high resolution A/D. If a large number of inputs must be monitored simultaneously in a system, the controlled timing relationship between the frequency output pulses and the user- supplied clock greatly simplifies this signal acquisition. Also, if the clock signal is provided by a VFC, the output frequency of the SVFC is proportional to the product of the two input voltages. Therefore, multiplication and A-to-D conversion on two signals are performed simultaneously. +VS 1 TRIM 2 TRIM 3 OP AMP OUT 4 OP AMP "–" 5 OP AMP "+" 6 10 VOLT INPUT 7 –VS 8 COMP REF 16 COMP "+" 15 COMP "–" 14 ANALOG GND 13 DIGITAL GND 12 FREQ OUT 11 CLOCK INPUT 10 COS 9 ONE SHOT AND "D" FLOP QCK D Q 1mA 20k Ω AD652 SYNCHRONOUS VOLTAGE-TO- FREQUENCY CONVERTER 5V REFERENCE Figure 2. CERDIP Pin Configuration The pinouts of the AD652 SVFC are shown in Figure 2 and Figure 3. A block diagram of the device configured as an SVFC, along with various system waveforms, is shown in Figure 4. OP AMP OUT 4 OP AMP "–" 5 OP AMP "+" 6 5V INPUT 7 10V INPUT 8 COMP "+" 18 COMP "–" 17 ANALOG GND 16 DIGITAL GND 15 FREQ OUT 14 9 10 11 12 13 3 2 1 20 19 1mA 5V REFERENCE NC = NO CONNECT AND "D" FLOP Q CK D Q ONE SHOT 10k Ω 10k Ω 16k Ω 4k Ω AD652 SYNCHRONOUS VOLTAGE-TO-FREQUENCY CONVERTER Figure 3. PLCC Pin Configuration Figure 4 shows the typical up-and-down ramp integrator output of a charge-balance VFC. After the integrator output has crossed the comparator threshold and the output of the AND gate has gone high, nothing happens until a negative edge of the clock comes along to transfer the information to the output of the D FLOP. At this point, the clock level is low, so the latch does not change state. When the clock returns high, the latch output goes high and drives the switch to reset the integrator; at the same time, the latch drives the AND gate to a low output state. On the very next negative edge of the clock, the low output state of the AND gate is transferred to the output of the D FLOP. When the clock returns high, the latch output goes low and drives the switch back into the Integrate mode. At the same time, the latch drives the AND gate to a mode where it truthfully relays the information presented to it by the comparator. Because the reset pulses applied to the integrator are exactly one clock period long, the only place where drift can occur is in a variation of the symmetry of the switching speed with temperature. Since each reset pulse is identical, the AD652 SVFC produces a very linear voltage-to-frequency transfer relation. Also, because all reset pulses are gated by the clock, there are no problems with dielectric absorption causing the duration of a reset pulse to be influenced by the length of time since the last reset. |
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