REV. 0

AD74111

–15–

DAC

DAC

ADC

ADC

1/

f

S

16 DCLKs

DFS

DIN

DOUT

Figure 24. Multiframe Sync 16-Bit Data Mode

Table III. Multiframe Sync Selection

CRD:9

CRD:3

CRC:2

MFS

DM/MM

DSP Mode

Operating Mode

Figure

10

0

16-Bit Data Mode

24

10

1

32-Bit Data Mode

22

11

0

16-Bit Mixed Mode

23

11

1

32-Bit Mixed Mode

21

Table IV. Control Register Map

Address (Binary)

Name

Description

Type

Width

Reset Setting

0 0 0 0

CRA

Control Register A

R/W

10

00h

0 0 0 1

CRB

Control Register B

R/W

10

00h

0 0 1 0

CRC

Control Register C

R/W

10

00h

0 0 1 1

CRD

Control Register D

R/W

10

08h or 09h

*

0 1 0 0

CRE

Control Register E

R/W

10

00h

0 1 0 1

CRF

Control Register F

R

10

00h

0 1 1 0

CRG

Control Register G

R/W

10

00h

*09h if DIN is low and 08h if DIN is high.

Table V. Control Word Descriptions

Bit

Field

Description

15

R/W

When this bit is high, the contents of the data field will be written to the register specified by the Address

Field. When this bit is low, a read of the register specified by the Address Field will occur at the next

sample interval; the contents of the Data Field are ignored.

14–11

Register Address

This 4-bit field is used to select one of the seven control registers of the AD74111.

10

Reserved

This bit is reserved and should always be programmed with zero.

9–0

Data Field

This 10-bit field holds the data that is to be written to or read from the register specified in the Address Field.