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UC3842BDG Datasheet(PDF) 8 Page - ON Semiconductor

Part No. UC3842BDG
Description  High Performance Current Mode Controllers
Download  22 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

UC3842BDG Datasheet(HTML) 8 Page - ON Semiconductor

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UC3842B, UC3843B, UC2842B, UC2843B
http://onsemi.com
8
OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost−effective
solution
with
minimal
external
components.
A
representative block diagram is shown in Figure 19.
Oscillator
The oscillator frequency is programmed by the values
chosen for the timing components RT and CT. It must also be
noted that the value of RT uniquely determines the
maximum duty ratio of UC384xx. The oscillator
configuration depicting the connection of the timing
components to the RT/CT pin of the controller is shown in
Figure 18. Capacitor CT gets charged from the Vref source,
through resistor RT to its peak threshold VRT/CT(peak),
typically 2.8 V. Upon reaching this peak threshold volage, an
internal 8.3 mA current source, Idischg, is enabled and the
voltage across CT begins to decrease. Once the voltage
across CT reaches its valley threshold, VRT/CT(valley),
typically 1.2 V, Idischg turns off. This allows capacitor CT to
charge up again from Vref. This entire cycle repeats, and the
resulting waveform on the RT/CT pin has a sawtooth shape.
Typical waveforms are shown in Figure 20.
The oscillator thresholds are temperature compensated to
within
±6% at 50 kHz
. Considering the general industry
trend of operating switching controllers at higher
frequencies, the UC384xx is guaranteed to operate within
±10% at 250 kHz. These internal circuit refinements
minimize variations of oscillator frequency and maximum
duty ratio.
The charging and discharging times of the timing
capacitor CT are calculated using Equations 1 and 2. These
equations do not take into account the propagation delays of
the internal comparator. Hence, at higher frequencies, the
calculated value of the oscillator frequency differs from the
actual value.
t
RT CT(chg) + RTCT ln
VRT CT(valley) * Vref
V
RT CT(peak) * Vref
(eq. 1)
t
RT CT(dischg) + RTCT ln
RTIdischg ) VRT CT(peak) * Vref
RTIdischg ) VRT CT(valley) * Vref
(eq. 2)
The maximum duty ratio, Dmax is given by Equation 3.
Dmax +
t
RT CT(chg)
t
RT CT(chg) ) tRT CT(dischg)
(eq. 3)
Substituting Equations 1 and 2 into Equation 3, and after
algebraic simplification, we obtain
Dmax +
ln
VRT CT(valley)*Vref
VRT CT(peak)*Vref
ln
VRT CT(valley)*Vref
VRT CT(peak)*Vref @
RTIdischg)VRT CT(peak)*Vref
RTIdischg)VRT CT(valley)*Vref
(eq. 4)
Clearly, the maximum duty ratio is determined by the
timing resistor RT. Therefore, RT is chosen such as to
achieve a desired maximum duty ratio. Once RT has been
selected, CT can now be chosen to obtain the desired
switching frequency as per Equation 5.
f +
1
RTCT ln
VRT CT(valley)*Vref
VRT CT(peak)*Vref @
RTIdischg)VRT CT(peak)*Vref
RTIdischg)VRT CT(valley)*Vref
(eq. 5)
Figure 2 shows the frequency and maximum duty ratio
variation versus RT for given values of CT. Care should be
taken to ensure that the absolute minimum value of RT
should not be less than 542
W. However, considering a 10%
tolerance for the timing resistor, the nearest available
standard resistor of 680
W is the absolute minimum that can
be used to guarantee normal oscillator operation. If a timing
resistor smaller than this value is used, then the charging
current through the RT, CT path will exceed the pulldown
(discharge) current and the oscillator will get permanently
locked/latched to an undefined state.
In many noise-sensitive applications it may be desirable
to frequency-lock the converter to an external system clock.
This can be accomplished by applying a clock signal to
the
circuit shown in Figure 22. For reliable synchronization, the
free-running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi-unit
synchronization is shown in Figure 23. By tailoring the
clock waveform, accurate Output duty ratio clamping can be
achieved.
Enable
Idischg
Vref
RT/CT
RT
CT
2.8 V
1.2 V
Figure 18. Oscillator Configuration


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