NCP374

http://onsemi.com

4

PIN FUNCTION DESCRIPTION

Pin

Pin

Name

Type

Description

1, 2

VBUS

POWER

VBUS voltage pins: must be hardwired together on the PCB.

These pins are connected to the VBUS connector, and are protected against positive and negative

overvoltage events.

A 1 mF low ESR ceramic capacitor, or larger, must be connected between these pins and GND.

3

GND

POWER

Ground

4

RES1

INPUT

Reserved pin. Must be connected to GND potential and used for IC test.

5

RES2

INPUT

Reserved pin. Must be connected to GND potential and used for IC test.

6

RES3

INPUT

Reserved pin. Must be connected to GND potential and used for IC test.

7

Ilim

OUTPUT

Current Limit Pin. This pin provides the reference, based on the internal band−gap voltage reference,

to limit the over current, across internal NMosFet. A 0.1% tolerance resistor shall be used to get the

highest accuracy of the Over Current Limit.

8

EN

INPUT

Enable Pin. In combination with DIR, the internal NMOSes are turned on if Battery is applied on the

IN pins. (See logic table)

In enable mode, the internal Over−Current protection is activated from IN to VBUS. When enable

mode is disabled, the NCP374 current consumption, into IN pin, is drastically decreased to limit cur-

rent leakage of the self powered devices.

9

DIR

INPUT

Direct Mode pin. This pin can be used, in combination with Enable pin, for the front end protection

applications like wireless devices. In this case, the part can be used as +/− OVP only. See logic

table.

10

FLAG

OUTPUT

Fault indication pin.

This pin allows an external system to detect fault condition.

The FLAG pin goes low when input voltage exceeds OVLO threshold or drops below UVLO

threshold (charging mode), charge current from IN to VBus exceeds current limit or internal temper-

ature exceeds thermal shutdown limit.

Since the FLAG pin is open drain functionality, an external pull up resistor to VBat must be added

(10 kW minimum value).

11

IN

POWER

IN pin. In Front end application this pin is connected to charger device input or PMIC input.

In host application, this pin is connected to upstream DCDC. This pin is used as power supply of the

core and current from IN to VBUS is then limited to the external

12

NC

NA

Not internally connected. Can be connected to any potential.

13

PAD1

POWER

Drain connection of the back to back MOSFET’s. This exposed pad mustn’t be connected to any

other potential and must be used for thermal dissipation of the internal MOSFETs.