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Motorola TMOS Power MOSFET Transistor Device Data

Designer's™ Data Sheet

High Density Power FET

DPAK for Surface Mount

N–Channel Enhancement–Mode Silicon Gate

This advanced HDTMOS power FET is designed to withstand

high energy in the avalanche and commutation modes. This new

energy efficient design also offers a drain–to–source diode with a

fast recovery time. Designed for low voltage, high speed switching

applications in power supplies, converters and PWM motor

controls, these devices are particularly well suited for bridge circuits

where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected

voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Dis-

crete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• IDSS and VDS(on) Specified at Elevated Temperature

• Surface Mount Package Available in 16 mm, 13–inch/2500

Unit Tape & Reel, Add T4 Suffix to Part Number

Rating

Symbol

Value

Unit

Drain–Source Voltage

VDSS

30

Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ)

VDGR

30

Vdc

Gate–Source Voltage — Continuous

VGS

VGSM

±15

± 20

Vdc

Vpk

Drain Current — Continuous

°C

ID

ID

IDM

20

16

60

Adc

Apk

Total Power Dissipation

Derate above 25

°C

Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size

PD

74

0.6

1.75

Watts

W/

°C

Operating and Storage Temperature Range

TJ, Tstg

– 55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)

EAS

200

mJ

Thermal Resistance — Junction to Case

R

θJC

R

θJA

R

θJA

1.67

100

71.4

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

″ from case for 10 seconds

TL

260

°C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Order this document

by MTD20N03HDL/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

© Motorola, Inc. 1995

MTD20N03HDL

TMOS POWER FET

LOGIC LEVEL

20 AMPERES

30 VOLTS

RDS(on) = 0.035 OHM

Motorola Preferred Device

™

D

S

G

CASE 369A–13, Style 2

DPAK