AD5504

Data Sheet

Rev. B | Page 6 of 20

TIMING CHARACTERISTICS

Table 4.

Parameter

Limit1

Unit

Test Conditions/Comments

60

ns min

SCLK cycle time

10

ns min

SCLK high time

10

ns min

SCLK low time

25

ns min

SYNC falling edge to SCLK rising edge setup time

15

ns min

Data setup time

5

ns min

Data hold time

0

ns min

SCLK falling edge to SYNC rising edge

20

ns min

Minimum SYNC high time

20

ns min

LDAC pulse width low

50

ns min

SCLK falling edge to LDAC rising edge

15

ns min

CLR pulse width low

100

ns typ

CLR pulse activation time

20

μs typ

ALARM clear time

110

ns min

SCLK cycle time in read mode

t153

55

ns max

SCLK rising edge to SDO valid

t163

25

ns min

SCLK to SDO data hold time

t174

50

μs max

Power-on reset time (this is not shown in the timing diagrams)

t185

50

μs max

Power-on time (this is not shown in the timing diagrams)

5

μs typ

ALARM clear to output amplifier turn on (this is not shown in the timing

diagrams)

1

2

Maximum SCLK frequency is 16.667 MHz.

3

Under load conditions shown in Figure 2.

4

5

Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.

2

200µA

200µA

TO OUTPUT

PIN

50pF

Figure 2. Load Circuit for SDO Timing Diagram