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AD5303 Datasheet(PDF) 19 Page - Analog Devices |
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AD5303 Datasheet(HTML) 19 Page - Analog Devices |
19 / 28 page AD5303/AD5313/AD5323 Rev. B | Page 19 of 28 POWER-DOWN MODES The AD5303/AD5313/AD5323 have very low power consump- tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word. Table 7 shows how the state of the bits corresponds to the mode of operation of that particular DAC. Table 7. PD1/PD0 Operating Modes PD1 PD0 Operating Mode 0 0 Normal operation 0 1 Power-down (1 kΩ load to GND) 1 0 Power-down (100 kΩ load to GND) 1 1 Power-down (high impedance output) When both bits are set to 0, the DACs work normally with their normal power consumption of 300 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different power-down options. The output is connected internally to GND through either a 1 kΩ resistor or a 100 kΩ resistor, or it is left in a high impedance state (three- state). The output stage is illustrated in Figure 34. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V (see Figure 24 for a plot). The software power-down modes programmed by PD0 and PD1 are overridden by the PD pin. Taking this pin low puts both DACs into power-down mode simultaneously and both outputs are put into a high impedance state. If PD is not used, it should be tied high. RESISTOR STRING DAC AMPLIFIER VOUT POWER-DOWN CIRCUITRY RESISTOR NETWORK Figure 34. Output Stage During Power-Down |
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