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DG406DN Datasheet(PDF) 1 Page - Vishay Siliconix |
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DG406DN Datasheet(HTML) 1 Page - Vishay Siliconix |
1 / 16 page Vishay Siliconix DG406, DG407 Document Number: 70061 S11-0179-Rev. J, 07-Feb-11 www.vishay.com 1 16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers FEATURES • Low on-resistance - RDS(on): 50 • Low charge injection - Q: 15 pC • Fast transition time - tTRANS: 200 ns • Low power: 0.2 mW • Single supply capability • 44 V supply max. rating BENEFITS • Higher accuracy • Reduced glitching • Improved data throughput • Reduced power consumption • Increased ruggedness • Wide supply ranges: ± 5 V to ± 20 V APPLICATIONS • Data acquisition systems • Audio signal routing • Medical instrumentation • ATE systems • Battery powered systems • High-rel systems • Single supply systems DESCRIPTION The DG406 is a 16 channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. The DG407 selects one of eight differential inputs to a common differential output. Break-before-make switching action protects against momentary shorting of inputs. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. Applications for the DG406, DG407 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. Designed in the 44 V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 V, allowing operation with ± 20 V supplies. Additionally single (12 V) supply operation is allowed. An epitaxial layer prevents latchup. For applications information please request documents 70601 and 70604. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION * Pb containing terminations are not RoHS compliant, exemptions may apply V+ S11 S10 S9 NC A3 D S2 S1 GND A1 A2 NC Dual-In-Line and SOIC Wide-Body A0 EN V- NC S8 S16 S7 S15 S6 S14 S5 S13 S4 S12 S3 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 Top View 920 10 19 11 12 18 17 13 16 14 15 DG406 Decoders/Drivers DG407 V+ S3b S2b S1b NC NC Da S2a S1a GND A1 A2 Db Dual-In-Line and SOIC Wide-Body A0 EN V- NC S8a S8b S7a S7b S6a S6b S5a S5b S4a S4b S3a 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 Top View 92 20 10 19 11 12 18 17 13 16 14 15 Decoders/Drivers Available Pb-free RoHS* COMPLIANT |
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