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EPF10K50V Datasheet(PDF) 59 Page - Altera Corporation |
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EPF10K50V Datasheet(HTML) 59 Page - Altera Corporation |
59 / 128 page Altera Corporation 59 FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 28. Synchronous Bidirectional Pin External Timing Model Tables 32 through 36 describe the FLEX 10K device internal timing parameters. These internal timing parameters are expressed as worst-case values. Using hand calculations, these parameters can be used to estimate design performance. However, before committing designs to silicon, actual worst-case performance should be modeled using timing simulation and analysis. Tables 37 through 38 describe FLEX 10K external timing parameters. PRN CLRN DQ PRN CLRN DQ PRN CLRN DQ Dedicated Clock Bidirectional Pin Output Register tINSUBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINHBIDIR OE Register Input Register Table 32. LE Timing Microparameters (Part 1 of 2) Note (1) Symbol Parameter Conditions tLUT LUT delay for data-in tCLUT LUT delay for carry-in tRLUT LUT delay for LE register feedback tPACKED Data-in to packed register delay tEN LE register enable delay tCICO Carry-in to carry-out delay tCGEN Data-in to carry-out delay tCGENR LE register feedback to carry-out delay tCASC Cascade-in to cascade-out delay tC LE register control signal delay tCO LE register clock-to-output delay tCOMB Combinatorial delay |
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