LP2998

GND

47 PF

+

+

+

330 PF

SD

SD

+

330 PF

0.01 PF

LP2998

GND

+

+

+

SD

SD

LP2998

SNVS521I – DECEMBER 2007 – REVISED APRIL 2013

www.ti.com

OUTPUT CAPACITOR SELECTION

For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in

Figure 27 can be implemented.

Figure 27. Typical SSTL-2 Application Circuit

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection

can be varied depending on the number of lines terminated and the maximum load transient. However, with

multiple bulk capacitors in addition to high frequency decoupling. Figure 28 depicts an example circuit where 2

electrolytic capacitors are typically used for their low ESR and low cost.

Figure 28. Typical SSTL-2 Application Circuit for Motherboards

In most PC applications, an extensive amount of decoupling is required because of the long interconnects

encountered with the DDR-SDRAM DIMMs mounted on modules. As a result, bulk aluminum electrolytic

capacitors in the range of 1000uF are typically used.

PCB Layout Considerations

1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.

motherboard applications an ideal location would be at the center of the termination bus.

most accurate point for creating the reference voltage.

4. For improved thermal performance excessive top side copper should be used to dissipate heat from the

package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these

can be located underneath the package if manufacturing standards permit.

16

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