ADN2818ACPZ datasheet(19/40 Pages) AD

Part #	ADN2818ACPZ

Description	Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

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Data Sheet

ADN2817/ADN2818

Rev. E | Page 19 of 40

JITTER SPECIFICATIONS

The ADN2817/ADN2818 CDR is designed to achieve the best

bit error rate (BER) performance and exceeds the jitter transfer,

generation, and tolerance specifications proposed for SONET/SDH

equipment defined in the Telcordia® Technologies specification.

Jitter is the dynamic displacement of digital signal edges from

their long-term average positions, measured in unit intervals

(UI), where 1 UI = 1 bit period. Jitter on the input data can cause

dynamic phase errors on the recovered clock sampling edge. Jitter

on the recovered clock causes jitter on the retimed data.

The following sections briefly summarize the specifications

of jitter generation, transfer, and tolerance in accordance with

the Telcordia document (GR-253-CORE, Issue 3, September

2000) for the optical interface at the equipment level and the

ADN2817/ADN2818 performance with respect to those

specifications.

JITTER GENERATION

The jitter generation specification limits the amount of jitter

that can be generated by the device with no jitter and wander

applied at the input. For OC-48 devices, the band-pass filter

has a 12 kHz high-pass cutoff frequency with a roll-off of

20 dB/decade and a low-pass cutoff frequency of at least

20 MHz. The jitter generated must be less than 0.01 UI rms

and must be less than 0.1 UI p-p.

JITTER TRANSFER

The jitter transfer function is the ratio of the jitter on the output

signal to the jitter applied on the input signal vs. the frequency.

This parameter measures the limited amount of the jitter on

an input signal that can be transferred to the output signal

(see Figure 26).

0.1

ACCEPTABLE

RANGE

fC

JITTER FREQUENCY (kHz)

SLOPE = –20dB/DECADE

Figure 26. Jitter Transfer Curve

JITTER TOLERANCE

The jitter tolerance is defined as the peak-to-peak amplitude of

the sinusoidal jitter applied on the input signal, which causes a

1 dB power penalty. This is a stress test intended to ensure that

no additional penalty is incurred under the operating conditions

(see Figure 27).

15.00

1.50

0.15

f0

f1

f2

f3

f4

JITTER FREQUENCY (kHz)

SLOPE = –20dB/DECADE

Figure 27. SONET Jitter Tolerance Mask

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