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ADN2817ACPZ-RL Datasheet(PDF) 11 Page - Analog Devices

Part # ADN2817ACPZ-RL
Description  Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN2817ACPZ-RL Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
ADN2817/ADN2818
Rev. E | Page 11 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BERMODE
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
NOTES
1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VEE.
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
ADN2817/
ADN2818
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
BERMODE
DI
Set this pin to logic low to enable analog voltage output mode for BER monitor.
2
VCC
P
Power for Input Stage, LOS.
3
VREF
AO
Internal VREF Voltage. Decouple to ground with a 0.1 µF capacitor.
4
NIN
AI
Differential Data Input. CML.
5
PIN
AI
Differential Data Input. CML.
6
SLICEP
AI
Differential Slice Level Adjust Input.
7
SLICEN
AI
Differential Slice Level Adjust Input.
8
VEE
P
GND for the Limiting Amplifier, LOS.
9
THRADJ
AI
LOS Threshold Setting Resistor.
10
REFCLKP
DI
Differential REFCLK Input. 10 MHz to 200 MHz.
11
REFCLKN
DI
Differential REFCLK Input. 10 MHz to 200 MHz.
12
VCC
P
VCO Power.
13
VEE
P
VCO Ground.
14
CF2
AO
Frequency Loop Capacitor.
15
CF1
AO
Frequency Loop Capacitor.
16
LOL
DO
Loss of Lock Indicator. Active high, LVTTL.
17
VEE
P
FLL Detector Ground.
18
VCC
P
FLL Detector Power.
19
SADDR5
DI
Slave Address Bit 5.
20
SCK
DI
I2C Clock Input.
21
SDA
DI
I2C Data Input.
22
LOS
DO
Loss of Signal Detect Output. Active high, LVTTL.
23
VEE
P
Output Buffer, I2C Ground.
24
VCC
P
Output Buffer, I2C Power.
25
CLKOUTN
DO
Differential Recovered Clock Output. CML.
26
CLKOUTP
DO
Differential Recovered Clock Output. CML.
27
SQUELCH
DI
Disable Clock and Data Outputs. Active high, LVTTL.
28
DATAOUTN
DO
Differential Recovered Data Output. CML.
29
DATAOUTP
DO
Differential Recovered Data Output. CML.
30
VEE
P
Phase Detector, Phase Shifter Ground.
31
VCC
P
Phase Detector, Phase Shifter Power.
32
VBER
AO
This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE.
EP
EPAD
P
Exposed Paddle. The Exposed paddle on the bottom of the package must be connected
to VEE.
1
P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.


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