ADN2817ACPZ-RL datasheet(31/40 Pages) AD

Part #	ADN2817ACPZ-RL

Description	Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

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Data Sheet

ADN2817/ADN2818

Rev. E | Page 31 of 40

Transmission Lines

Use of 50 Ω transmission lines is required for all high frequency

input and output signals to minimize reflections: PIN, NIN,

CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also

REFCLKP, REFCLKN, if using a high frequency reference clock,

such as 155 MHz). It is also necessary for the PIN/NIN input

traces to be matched in length, and the CLKOUTP, CLKOUTN,

DATAOUTP, and DATAOUTN output traces to be matched

in length to avoid skew between the differential traces.

All high speed CML outputs (CLKOUTP, CLKOUTN, DATAOUTP,

and DATAOUTN) require 100 Ω back termination chip resis-

tors connected between the output pin and VCC. Place these

resistors as close as possible to the output pins. These 100 Ω

resistors are in parallel with on-chip 100 Ω termination resistors

to create a 50 Ω back termination (see Figure 37).

The high speed inputs (PIN and NIN) are internally terminated

with 50 Ω to an internal reference voltage (see Figure 38). A 0.1 μF

capacitor is recommended between VREF, Pin 3, and GND to

provide an ac ground for the inputs.

As with any high speed mixed-signal design, take care to keep

all high speed digital traces away from sensitive analog nodes.

50Ω

VTERM

50Ω

0.1µF

100Ω

VCC

100Ω

VCC

ADN2817/ADN2818

Figure 37. Typical ADN2817/ADN2818 Applications Circuit

50Ω

2.5V

ADN2817/ADN2818

VCC

TIA

CIN

NIN

3kΩ

VREF

0.1µF

TIA

Figure 38. ADN2817/ADN2818 AC-Coupled Input Configuration

Soldering Guidelines for Lead Frame Chip Scale Package

The lands on the 32-lead LFCSP are rectangular. The printed

circuit board pad for these should be 0.1 mm longer than the

package land length, and 0.05 mm wider than the package land

width. Center the land on the pad to ensure that the solder joint

size is maximized. The bottom of the lead frame chip scale package

has a central exposed pad. The pad on the printed circuit board

should be at least as large as this exposed pad. The user must

connect the exposed pad to VEE using plugged vias to prevent

solder from leaking through the vias during reflow. This ensures a

solid connection from the exposed pad to VEE.

Choosing AC Coupling Capacitors

AC coupling capacitors at the input (PIN, NIN) and output

(DATAOUTP, DATAOUTN) of the ADN2817/ADN2818

must be chosen such that the device works properly over the

full range of data rates used in the application. When choosing

the capacitors, the time constant formed with the two 50 Ω

resistors in the signal path must be considered. When a large

number of consecutive identical digits (CIDs) are applied, the

capacitor voltage can droop due to baseline wander (see Figure 39),

causing pattern dependent jitter (PDJ).

The user must determine how much droop is tolerable and choose

an ac coupling capacitor based on that amount of droop. The

amount of PDJ can then be approximated based on the capacitor

selection. The actual capacitor value selection may require some

trade-offs between droop and PDJ.

For example, assuming that 2% droop can be tolerated, the

maximum differential droop is 4%. Normalizing to peak-to-

peak voltage,

Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e–t/τ) ; therefore, τ = 12t

where:

τ is the RC time constant (C is the ac coupling capacitor, and

R = 100 Ω seen by C).

t is the total discharge time, which is equal to n.

n is the number of CIDs.

T is the bit period.

Calculate the capacitor value by combining the equations

for τ and t.

C = 12nT/R

When the capacitor value is selected, the PDJ can be

approximated as

PDJps p-p = 0.5tr(1 − e(−nT/RC))/0.6

where:

PDJps p-p is the amount of pattern-dependent jitter allowed;

<0.01 UI p-p typical.

tr is the rise time, which is equal to 0.22/BW, where BW ≈ 0.7

(bit rate).

Note that this expression for tr is accurate only for the inputs.

The output rise time for the ADN2817/ADN2818 is ~100 ps

regardless of data rate.

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