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ADMC331BST Datasheet(PDF) 3 Page - Analog Devices |
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ADMC331BST Datasheet(HTML) 3 Page - Analog Devices |
3 / 36 page ADMC331 –3– REV. B TIMING PARAMETERS Parameter Min Max Unit Clock Signals tCK is defined as 0.5 tCKI. The ADMC331 uses an input clock with a frequency equal to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain specification value. Example: tCKH = 0.5 tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns. Timing Requirements: tCKI CLKIN Period 76.9 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns Switching Characteristics: tCKL CLKOUT Width Low 0.5 tCK – 10 ns tCKH CLKOUT Width High 0.5 tCK – 10 ns tCKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement: tRSP RESET Width Low 5 tCK 1 ns PWM Shutdown Signals Timing Requirement: tPWMTPW PWMTRIP Width Low 2 tCK ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT tCKOH tCKI tCKIH tCKH tCKL tCKIL Figure 1. Clock Signals |
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