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LTC1296 Datasheet(PDF) 19 Page - Linear Technology |
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LTC1296 Datasheet(HTML) 19 Page - Linear Technology |
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19 / 28 page  19 LTC1293/LTC1294/LTC1296 129346fs S APPLICATI I FOR ATIO Source Resistance The analog inputs of the LTC1293/4/6 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON). CIN gets switched between (+) and (–) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time. “+” Input Settling The input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 8). The sample period 2 1/2 CLK cycles before a conversion starts. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 2.5 µs RSOURCE+ < 1.5kΩ Ω Ω Ω Ω and C1 < 20pF will provide adequate settling time. “–” Input Settling At the end of the sample phase the input capacitor switches to the “-” input and the conversion starts (see Figure 8). During the conversion, the “+” input voltage is effectively “held” by the sample and hold and will not affect the conversion result. It is critical that the “–” input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE– and C2 will improve settling time. If large “–” input source resistance must be used the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 1MHz, RSOURCE– < 250Ω Ω Ω Ω Ω and C2 < 20pF will provide adequate settling. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see Figure 8). Again the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle Figure 8. “+” and “–” Input Settling Windows DIN CLK START HI-Z LTC1293 F08 CS 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME tSMPL (+) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT SGL/ DIFF MSBF PS DOUT B11 SAMPLE HOLD |
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