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AD1852JRSZRL Datasheet(PDF) 7 Page - Analog Devices |
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AD1852JRSZRL Datasheet(HTML) 7 Page - Analog Devices |
7 / 20 page AD1852 Rev. A | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND 1 MCLK 2 CLATCH 3 CCLK 4 DVDD 28 SDATA 27 BCLK 26 LRCLK 25 CDATA 5 NC 6 192/48 7 RESET 24 MUTE 23 ZEROL 22 ZEROR 8 IDPM0 21 DEEMP 9 IDPM1 20 96/48 10 FILTB 19 AGND 11 AVDD 18 OUTR+ 12 OUTL+ 17 OUTR– 13 OUTL– 16 FILTER 14 AGND 15 TOP VIEW (Not to Scale) AD1852 Figure 2. Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Input/Output Description 1 DGND I Digital Ground. 2 MCLK I Master Clock Input. Connect to an external clock source running at either 256 fS, 384 fS, 512 fS, 768 fS, or 1024 fS. 3 CLATCH I Latch Input for SPI Control Data Port. This input is rising-edge sensitive. 4 CCLK I SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. 5 CDATA I SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in the SPI Register Definitions section. 6 NC No Connect. 7 192/48 I 192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz. When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register. 8 ZEROR O Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input for more than 1024 LR clock cycles. 9 DEEMP I De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI control register. 10 96/48 I 96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz. When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register. 11, 15 AGND I Analog Ground. 12 OUTR+ O Right Channel Positive Line Level Analog Output. 13 OUTR− O Right Channel Negative Line Level Analog Output. 14 FILTR O Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 μF and 0.1 μF capacitors to the AGND. 16 OUTL− O Left Channel Negative Line Level Analog Output. 17 OUTL+ O Left Channel Positive Line Level Analog Output. 18 AVDD I Analog Power Supply. Connect this pin to the analog 5 V supply. 19 FILTB Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15). 20 IDPM1 I Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes. 21 IDPM0 I Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes. 22 ZEROL O Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input for more than 1024 LR clock cycles. 23 MUTE I Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation. 24 RESET I Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. For normal operation, assert this pin high. |
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