AD1852JRSZRL datasheet(4/20 Pages) AD

Part #	AD1852JRSZRL

Description	Stereo, 24-Bit, 192 kHz, Multibit, Sigma-Delta DAC

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Manufacturer	AD [Analog Devices]

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AD1852

Rev. A | Page 4 of 20

DIGITAL I/O (0°C TO 70°C)

Table 3.

Parameter

Min

Typ

Max

Unit

Input Voltage High (VIH)

2.2

V

Input Voltage Low (VIL)

0.8

V

Input Leakage (IIH at VIH = 2.4 V)

10

μA

Input Leakage (IIL at VIL = 0.8 V)

10

μA

High Level Output Voltage (VOH), IOH = 1 mA

2.0

V

Low Level Output Voltage (VOL), IOL = 1 mA

0.4

V

Input Capacitance

20

pF

TEMPERATURE RANGE

Table 4.

Parameter

Min

Typ

Max

Unit

Specifications Guaranteed

25

°C

Functionality Guaranteed

0

70

°C

Storage

−55

+150

°C

POWER

Table 5.

Parameter

Min

Typ

Max

Unit

SUPPLIES

Voltage, Analog and Digital

4.50

5

5.50

V

Analog Current

33

40

mA

Analog Current—RESET

32

46

mA

Digital Current

20

30

mA

Digital Current—RESET

27

37

mA

DISSIPATION

Operation—Both Supplies

265

mW

Operation—Analog Supply

165

mW

Operation—Digital Supply

100

mW

POWER SUPPLY REJECTION RATIO

1 kHz, 300 mV p-p Signal at Analog Supply Pins

−60

dB

20 kHz, 300 mV p-p Signal at Analog Supply Pins

−50

dB

DIGITAL FILTER CHARACTERISTICS

Table 6.

Sample Rate (kHz)

Pass Band (kHz)

Stop Band (kHz)

Stop-Band Attenuation (dB)

Pass-Band Ripple (dB)

44.1

DC − 20

24.1 − 328.7

110

±0.0002

48

DC − 21.8

26.23 − 358.28

110

±0.0002

96

DC − 39.95

56.9 − 327.65

115

±0.0005

192

DC − 87.2

117 − 327.65

95

+0/−0.04 (DC − 21.8 kHz)

+0/−0.5 (DC − 65.4 kHz)

+0/−1.5 (DC − 87.2 kHz)

GROUP DELAY

Table 7.

Chip Mode

Group Delay Calculation

fS (kHz)

Group Delay (μs)

INT8× Mode

5553/(128 × fS)

48

903.8

INT4× Mode

5601/(64 × fS)

96

911.6

INT2× Mode

5659/(32 × fS)

192

921

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