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LT124XIS8 Datasheet(PDF) 10 Page - Linear Technology |
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LT124XIS8 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  LT1241 Series 10 S APPLICATI I FOR ATIO Undervoltage Lockout The LT1241 series devices incorporate an undervoltage lockout comparator which prevents the internal reference circuitry and the output from starting up until the supply voltage reaches the start-up threshold voltage. The quies- cent current, below the start-up threshold, has been reduced to less than 250 µA (170µA typ.) to minimize the power loss due to the bleed resistor used for start-up in off-line converters. In undervoltage lockout both VREF (Pin 8) and the output (Pin 6) are actively pulled low by Darlington connected PNP transistors. They are designed to sink a few milliamps of current and will pull down to about 1V. The pull-down transistor at the reference pin can be used to reset the external soft start capacitor. The pull- down transistor at the output eliminates the external pull- down resistor required, with earlier devices, to hold the external MOSFET gate low during undervoltage lockout. Output The LT1241 series devices incorporate a single high current totem pole output stage. This output stage is capable of driving up to ±1A of output current. Cross- conduction current spikes in the output totem pole have been eliminated. This device is primarily intended for driving MOSFET switches. Rise time is typically 40ns and fall time is typically 30ns when driving a 1.0nF load. A clamp is built into the device to prevent the output from rising above 18V in order to protect the gate of the MOSFET switch. The output is actively pulled low during undervoltage lockout by a Darlington PNP. This PNP is designed to sink several milliamps and will pull the output down to approxi- mately 1V. This active pull-down eliminates the need for an external resistor which was required in older designs. The output pin of the device connects directly to the emitter of the upper NPN drive transistor and the collector of the lower NPN drive transistor in the totem pole. The collector of the lower transistor, which is n-type silicon, forms a p-n junction with the substrate of the device. This junction is reverse biased during normal operation. In some applications the parasitic LC of the external MOSFET gate can ring and pull the OUTPUT pin below ground. If the OUTPUT pin is pulled negative by more than a diode drop the parasitic diode formed by the collector of the output NPN and the substrate will turn on. This can cause erratic operation of the device. In these cases a Schottky clamp diode is recommended from the output to ground. Reference The internal reference of the LT1241 series devices is a 5V bandgap reference, trimmed to within ±1% initial toler- ance. The reference is used to power the majority of internal logic and the oscillator circuitry. The oscillator charging current is supplied from the reference. The feedback pin voltage and the clamp level for the current sense comparator are derived from the reference voltage. The reference can supply up to 20mA of current to power external circuitry. Note that using the reference in this manner, as a voltage regulator, will significantly increase power dissipation in the device which will reduce the useful operating ambient temperature range. Design/Layout Considerations LT1241 series devices are high speed circuits capable of generating pulsed output drive currents of up to 1A peak. The rise and fall time for the output drive current is in the range of 10ns to 20ns. High speed circuit techniques must be used to insure proper operation of the device. Do not attempt to use Proto-boards or wire-wrap techniques to breadboard high speed switching regulator circuits. They will not work properly. Printed circuit layouts should include separate ground paths for the voltage feedback network, oscillator capaci- tor, and switch drive current. These ground paths should be connected together directly at the ground pin (Pin 5) of the LT124X. This will minimize noise problems due to pulsed ground pin currents. VCC should be bypassed, with a minimum of 0.1 µF, as close to the device as possible. High current paths should be kept short and they should be separated from the feedback voltage network with shield traces if possible. |
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