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AD2S82AJP Datasheet(PDF) 2 Page - Analog Devices

Part No. AD2S82AJP
Description  Variable Resolution, Monolithic Resolver-to-Digital Converters
Download  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD2S82AJP Datasheet(HTML) 2 Page - Analog Devices

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AD2S81A/AD2S82A–SPECIFICATIONS
AD2S81A
AD2S82A
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
SIGNAL INPUTS
Frequency
400
20,000
50
20,000
Hz
Voltage Level
1.8
2.0
2.2
1.8
2.0
2.2
V rms
Input Bias Current
60
150
60
150
nA
Input Impedance
1.0
1.0
M
Maximum Voltage
±8
±8V pk
REFERENCE INPUT
Frequency
400
20,000
50
20,000
Hz
Voltage Level
1.0
8.0
1.0
8.0
V pk
Input Bias Current
60
150
60
150
nA
Input Impedance
1.0
1.0
M
CONTROL DYNAMICS
Repeatability
1
1
LSB
Allowable Phase Shift
(Signals to Reference)
–10
+10
–10
+10
Degrees
Tracking Rate
10 Bits
1040
rps
12 Bits
260
260
rps
14 Bits
65
rps
16 Bits
16.25
rps
Bandwidth1
User Selectable
ACCURACY
Angular Accuracy
H
22 + 1 LSB
arc min
J
30 + 1 LSB
8 + 1 LSB
arc min
K
4 + 1 LSB
arc min
L
2 + 1 LSB
arc min
Monotonicity
Guaranteed Monotonic
Missing Codes (16-Bit Resolution) J, K
4
Codes
L
1
Code
VELOCITY SIGNAL
Linearity
Over Full Range
±1
3
±1
3
% FSD
Reversion Error
±2
±2
% FSD
DC Zero Offset
2
66
mV
DC Zero Offset Tempco
–22
–22
µV/°C
Gain Scaling Accuracy
10
10
% FSD
Output Voltage
1 mA Load
±8
±9
±10.5
±8
±9
±10.5
V
Dynamic Ripple
Mean Value
1.5
1.5
% rms O/P
Output Load
1.0
1.0
k
INPUT/OUTPUT PROTECTION
Analog Inputs
Overvoltage Protection
±8
±8V
Analog Outputs
Short Circuit O/P Protection
±5.6
±8
±10.4
±5.6
±8
±10.4
mA
DIGITAL POSITION
Resolution
10, 12, 14 and 16
Output Format
Bidirectional Natural Binary
Load
3
3
LSTTL
INHIBIT
3
Sense
Logic LO to Inhibit
Time to Stable Data
600
600
ns
ENABLE
3
Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State
ENABLE/Disable Time
35
110
35
110
ns
BYTE SELECT3
Sense
Logic HI
MS Byte DB1–DB8,
(LS Byte DB9–DB16)4
Logic LO
LS Byte DB1–DB8,
(LS Byte DB9–DB16)4
Time to Data Available
60
140
60
140
ns
SHORT CYCLE INPUTS
4, 5
Internally Pulled High
(100 k
Ω) to +V
S
SC1
SC2
0
0
10 Bit
0
1
12 Bit
1
0
14 Bit
1
1
16 Bit
DATA LOAD4, 5
Sense
Internally Pulled High (100 k
Ω)
150
300
ns
to +VS; Logic LO Allows
Data to Be Loaded into the
Counters from the Data Lines
REV. B
–2–
(@ TA = +25 C, unless otherwise noted)


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