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AD2S82AJP Datasheet(PDF) 6 Page - Analog Devices

Part No. AD2S82AJP
Description  Variable Resolution, Monolithic Resolver-to-Digital Converters
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD2S82AJP Datasheet(HTML) 6 Page - Analog Devices

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REV. B
–6–
AD2S81A/AD2S82A
CONNECTING THE CONVERTER
The power supply voltages connected to +VS and –VS pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to VL can be +5 V dc to +VS.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +VS, –VS and ANALOG GND
adjacent to the converter. Recommended values are 100 nF
(ceramic) and 10
µF (tantalum). Also capacitors of 100 nF and
10
µF should be connected between +V
L and DIGITAL GND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and
COS inputs, REFERENCE I/P and SIGNAL GND as shown
in Figure 7 and described in the Connecting the Resolver
section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the resolver to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GND and ANALOG GND are connected internally.
ANALOG GND and DIGITAL GND must be connected
externally.
The external components required should be connected as
shown in Figures 1a and 1b.
SIN I/P
SIGNAL GND
COS I/P
ANALOG GND
RIPPLE CLK
+12V
–12V
COMP
DATA
LOAD
SC1
16 DATA BITS
BYTE
SELECT
BUSY
DIR
AC ERROR
O/P
VCO I/P
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
O/P
AD2S82A
INTEGRATOR
I/P
DIGITAL
GND
SC2
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
+5V
VCO
O/P
VCO
DATA TRANSFER
LOGIC
C1
C2
R1
R2
HP FILTER
R4
R3
C3
REFERENCE I/P
+12V
–12V
R8
OFFSET ADJUST
R5
C4
C5
BANDWIDTH
SELECTION
VELOCITY
SIGNAL
R6
R7
C6
TRACKING
RATE
SELECTION
R9
SEGMENT
SWITCHING
A2
A1
A3
ENABLE
INHIBIT
R-2R DAC
PHASE-SENSITIVE
DETECTOR
Figure 1a. AD2S82A Connection Diagram
SIN I/P
SIGNAL GND
COS I/P
RIPPLE CLK
+12V
–12V
8 DATA BITS
BYTE
SELECT
BUSY
DIR
AC ERROR
O/P
VCO I/P
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
O/P
AD2S81A
INTEGRATOR
I/P
DIGITAL
GND
+5V
VCO
DATA TRANSFER
LOGIC
C1
C2
R1
R2
HP FILTER
R4
R3
C3
REFERENCE I/P
+12V
–12V
R8
OFFSET ADJUST
R5
C4
C5
BANDWIDTH
SELECTION
VELOCITY
SIGNAL
R6
R7
C6
TRACKING
RATE
SELECTION
R9
SEGMENT
SWITCHING
A2
A1
A3
ENABLE
INHIBIT
R-2R DAC
PHASE-SENSITIVE
DETECTOR
OUTPUT DATA LATCH
16-BIT UP/DOWN COUNTER
Figure 1b. AD2S81A Connection Diagram


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