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NM34W02 Datasheet(PDF) 8 Page - Fairchild Semiconductor

Part No. NM34W02
Description  2K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com

NM34W02 Datasheet(HTML) 8 Page - Fairchild Semiconductor

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NM34W02 Rev. C.2
Device Addressing (Continued)
Slave Addresses (Figure 4).
Refer to the following table for Slave Address string details:
Page Block
1 (2K)
Write Operations
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the NM34W02 recognizes the start condi-
tion, the devices interfaced to the IIC bus wait for a slave address
to be transmitted over the SDA line. If the transmitted slave
address matches an address of one of the devices, the designated
slave pulls the line LOW with an acknowledge signal and awaits
further transmissions.
Byte Write
For a write operation a second address field is required which is
a byte address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page block of memory.
Upon receipt of the byte address the NM34W02 responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the NM34W02
begins the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the NM34W02 inputs are
disabled, and the device will not respond to any requests from the
master. Refer to
Figure 5 for the address, acknowledge and data
transfer sequence.
Page Write
The NM34W02 is capable of a sixteen byte page write operation.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte is
transferred, the master can transmit up to fifteen more bytes. After
the receipt of each byte, the NM34W02 will respond with an
After the receipt of each byte, the internal address counter
increments to the next address and the next SDA data is accepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will 'roll over'
and the previously written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to
Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation the NM34W02 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the NM34W02 is still busy with the write operation no ACK will
be returned. If the NM34W02 has completed the write operation
an ACK will be returned and the host can then proceed with the
next read or write operation.
Software Write Protect
Software write protection on the NM34W02 protects the first 128
bytes of the EEPROM memory. Software write protection is
implemented through a seperate register called the WRITE PRO-
TECT (WP) Register and writing to this WP register permanently
WRITE protects the memory. This WP register is a "one-time-
only-write" register. Once this register is written, it cannot be
erased. After the first WRITE to this register, all future access'
to this register are ignored as if an invalid IIC cycle occured.
To write protect, the user must perform a byte write to the WP
register. This will permanently disable programming to the first
128 bytes of memory.
Addressing the WP Register
Addressing the WP register is very similar to accessing any
memory array with the following difference:
Instead of the conventional "1010" IIC device address, the unused
IIC device address "0110" is used to access just the WP register.
Device address "1010" will be used for all the typical memory array
access. With this difference in place, accessing the WP register is
same as a typical IIC byte write cycle as described under "Write
Operations" section. All timing information and waveform details
remain the same. The "Byte Address" and the "Data" fields of the
Byte write cycle serve as place holders and can be of any value
(Don't Care). Refer to
Figure 7.
Hardware Write Protect
Programming of the memory will not take place if the WP pin of the
NM34W02 is connected to VCC, regardless of whether the soft-
ware write protect register has been implemented or not. The
NM34W02 will accept slave and word addresses; but if the
memory accessed is write protected by the WP pin, the NM34W02
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted. (Note: if the WP pin is set to VCC,
it will prevent the software write protect register from being
Device Type

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