Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

NM24WXX Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. NM24WXX
Description  2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
Download  14 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo 

NM24WXX Datasheet(HTML) 1 Page - Fairchild Semiconductor

 
Zoom Inzoom in Zoom Outzoom out
 1 / 14 page
background image
1
www.fairchildsemi.com
NM24Wxx Rev. C.2
PRELIMINARY
March 1999
© 1999 Fairchild Semiconductor Corporation
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to VCC. The memory then becomes unalterable
unless WP is switched to V
SS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Block Diagram
DS500074-1
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
16
YDEC
8
DATA REGISTER
XDEC
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
SLAVE ADDRESS
REGISTER &
COMPARATOR
START
STOP
LOGIC
START CYCLE
16/
32/
64/
128/
4
4
CK
DIN
R/W
LOAD
INC
SDA
VSS
VCC
WP
DOUT
A2
A1
A0
Device Address Bits
0/1/2/3
SCL
Features
s Hardware Write Protect for entire memory
s Low Power CMOS
200
µA active current typical
10
µA standby current typical
1
µA standby typical (L)
0.1
µA standby typical (LZ)
s IIC Compatible interface
— Provides bidirectional data transfer protocol
s Sixteen byte page write mode
— Minimizes total write time per byte
s Self timed write cycle
— Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0
° to +70°C
- Extended (E): -40
° to +85C
- Automotive (V): -40
° to +125°C


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn