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NM24WXX Datasheet(PDF) 6 Page - Fairchild Semiconductor

Part No. NM24WXX
Description  2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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NM24WXX Datasheet(HTML) 6 Page - Fairchild Semiconductor

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NM24Wxx Rev. C.2
Device
Address Pins
Memory Size
Number of
A0
A1
A2
Page Blocks
NM24W02
ADR
ADR
ADR
2048 Bits
1
NM24W04
NC
ADR
ADR
4096 Bits
2
NM24W08
NC
NC
ADR
8192 Bits
4
NM24W16
NC
NC
NC
16,384 Bits
8
ADR is the hardware address (VCC/1 or VSS/0) of the device(s) used.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM chip address. Table 1 shows the active
pins across the NM24Wxx device family.
TABLE 1.
Device
A0
A1
A2
Effects of Addresses
NM24W02
ADR
ADR
ADR 23 = 8; 8*x(1x2K)**=16K
NM24W04
x
ADR
ADR 22 = 4; 4*x(2x2K)**=16K
NM24W08
x
x
ADR 21 = 2; 2*x(4x2K)**=16K
NM24W16
x
x
x
20 = 1; 1*x(8x2K)**=16K
*
Max # of devices on bus
** Number of page blocks per density
WP Write Protection
If tied to VCC, PROGRAM operations onto memory will not be
executed. (Only READ operations are possible.) If tied to V
SS,
normal operation is enabled (READ/WRITE over the entire memory
is possible).
Device Operation
The NM24Wxx supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24Wxx will be considered a slave in
all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The NM24Wxx
continuously monitors the SDA and SCL lines for the start condi-
tion and will not respond to any command until this condition has
been met.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24Wxx to place the device in the
standby power mode.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to
Figure 3.
The NM24Wxx device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
the device and a write operation have been selected, the NM24Wxx
will respond with an acknowledge after the receipt of each
subsequent eight bit byte.
In the read mode the NM24Wxx slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.


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