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NM24WXX Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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NM24WXX Datasheet(HTML) 4 Page - Fairchild Semiconductor |
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4 www.fairchildsemi.com NM24Wxx Rev. C.2 AC Conditions of Test Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC x 0.5 Output Load 1 TTL Gate and CL = 100 pF Read and Write Cycle Limits (Standard and Low V CC Range 2.7V - 4.5V) Symbol Parameter 100 KHz 400 KHz Units Min Max Min Max fSCL SCL Clock Frequency 100 400 KHz T I Noise Suppression Time Constant at SCL, SDA Inputs (Minimum V IN 100 50 ns Pulse width) t AA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs tBUF Time the Bus Must Be Free before 4.7 1.3 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs t LOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs t SU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) t HD:DAT Data in Hold Time 0 0 ns t SU:DAT Data in Setup Time 250 100 ns tR SDA and SCL Rise Time 1 0.3 µs t F SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4.7 0.6 µs t DH Data Out Hold Time 300 50 ns tWR Write Cycle Time - NM24Wxx 10 10 ms (Note 3) - NM24WxxL, NM24WxxLZ 15 15 Note 3: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24Wxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. |
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