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NM24C32 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. NM24C32
Description  32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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NM24C32 Datasheet(HTML) 1 Page - Fairchild Semiconductor

 
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NM24C32 Rev. C.2
PRELIMINARY
March 1999
© 1999 Fairchild Semiconductor Corporation
NM24C32
32K-Bit Extended 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description:
The NM24C32 devices are 32,768 bits of CMOS nonvolatile
electrically erasable memory. These devices offer the designer
different low voltage and low power options, and they conform to
all specifications in the Extended IIC 2-wire protocol. Furthermore,
they are designed to minimize device pin count and simplify PC
board layout requirements.
The upper half of the memory can be disabled (Write Protection)
by connecting the WP pin to V
CC. This section of memory then
becomes ROM.
This communication protocol uses CLOCK (SCL) and DATA I/O
(SDA) lines to synchronously clock data between the master (for
example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Block Diagram
Features:
s Extended operating voltage 2.7V – 5.5V
s 400 KHz clock frequency (F) at 2.7V - 5.5V
s 200
µA active current typical
10
µA standby current typical
1
µA standby typical (L)
0.1
µA standby typical (LZ)
s IIC compatible interface
– Provides bidirectional data transfer protocol
s 32 byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
Typical write cycle time of 6ms
s Hardware write protect for upper block
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin SO, 8-pin DIP
s Low V
CC programming lockout (3.8V - on Standard VCC
devices only).
DS500073-1
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
YDEC
DATA REGISTER
XDEC
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
SLAVE ADDRESS
REGISTER &
COMPARATOR
START
STOP
LOGIC
WRITE
LOCKOUT
START CYCLE
CK
DIN
R/W
LOAD
INC
SDA
SCL
WP
VCC
DOUT
A2
A1
A0


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