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NM24C32 Datasheet(PDF) 6 Page - Fairchild Semiconductor

Part No. NM24C32
Description  32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com

NM24C32 Datasheet(HTML) 6 Page - Fairchild Semiconductor

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NM24C32 Rev. C.2
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V
to configure the EEPROM address for multiple device configura-
tion. A total of eight different devices can be attached to the same
SDA bus.
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the upper half
of the memory will not be executed. READ operations are always
If WP is tied to VSS, normal memory operation is enabled, READ/
WRITE over the entire memory array.
This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
The NM24C32xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as
a transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24C32xxx is considered a slave in
all applications.
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and reserved for indicating
start and stop conditions.
Refer to Figures 2 and 3.
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
NM24C32xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C32xxx to place the device in
the standby power mode.
Write Cycle Timing
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits. During the ninth clock
cycle the receiver will pull the SDA line LOW to acknowledge that
it received the eight bits of data. Refer to
Figure 4.
The NM24C32xxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
both the device and a WRITE operation have been selected, the
NM24C32xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the NM24C32xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.

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