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CAT25512VI-GT3 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT25512VI-GT3 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 16 page CAT25512 http://onsemi.com 8 Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3, 4, 6 and 7 can be written using the WRSR command. The internal programming for the SR bits will start after the low to high CS transition. The internal write cycle will last maximum 5 ms (tWC). It is recommended to avoid SR polling routine (through RDSR) while writing to the status register is in progress and insert a fixed delay of 5 ms before sending any other instruction to the CAT25512. Write Protection The Write Protect (WP) pin can be used to protect the Block Protect bits BP0 and BP1 against being inadvertently altered. When WP is low and the WPEN bit is set to “1”, write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to “0”. The WP input timing is shown in Figure 8. Figure 7. WRSR Timing 01 2 3 4 5 6 7 8 10 911 12 13 14 SCK SI MSB HIGH IMPEDANCE DATA IN 15 SO 7 6 5 4 3 2 10 00 0 0 0 0 0 1 OPCODE Dashed Line = mode (1, 1) CS Figure 8. WP Timing SCK WP Dashed Line = mode (1, 1) WP CS tWPH tWPS |
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