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ISO7242ADWG4 Datasheet(PDF) 6 Page - Texas Instruments |
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ISO7242ADWG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 21 page ISO7240A ISO7241A ISO7242A SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Quiescent 0.5 1 ISO7240A VI = VCC or 0 V, All channels, no load, EN2 at 3 V mA 1 Mbps 1 2 Quiescent 4 7 ICC1 ISO7241A VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA 1 Mbps 4 7 Quiescent 6 10 ISO7242A VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA 1 Mbps 6 10 Quiescent 15 22 ISO7240A VI = VCC or 0 V, All channels, no load, EN2 at 3 V mA 1 Mbps 16 22 Quiescent 13 20 ICC2 ISO7241A VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA 1 Mbps 13 20 Quiescent 10 16 ISO7242A VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA 1 Mbps 10 16 ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, Single channel 0 mA ISO7240A VCC – 0.4 IOH = –4 mA, See Figure 1 VOH High-level output voltage ISO724x (5-V side) VCC – 0.8 V IOH = –20 mA, See Figure 1 VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 VOL Low-level output voltage V IOL = 20 mA, See Figure 1 0.1 VI(HYS) Input voltage hysteresis 150 mV IIH High-level input current 10 IN from 0 V to VCC mA IIL Low-level input current –10 CI Input capacitance to IN at VCC, VI = 0.4 sin (4E6pt) 2 pF ground Common-mode transient VI = VCC or 0 V, See Figure 4 CMTI 25 50 kV/ms immunity (1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH, tPHL Propagation delay 40 100 See Figure 1 ns PWD Pulse-width distortion(1) |tPHL – tPLH| 11 2.5 tsk(o) Channel-to-channel output skew (2) ns 0 1 tr Output signal rise time 2 See Figure 1 ns tf Output signal fall time 2 tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 See Figure 2 ns tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 12 ms (1) Also known as pulse skew (2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. 6 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Not Recommended for New Designs |
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