IA64250

Data Sheet

Histogram/Hough Transform Processor

August 19, 2008

IA211011114-01

http://www.Innovasic.com

Customer Support:

Page 11 of 24

1-888-824-4184

io(1:0) Control the operations of the ACC and LUT RAMs during I/O mode (when the

STARTIOn signal has been asserted).

io0

io1

FUNCTION

0

0

1

1

0

1

0

1

transfer data from the ACC RAM to the LUT RAM

read the ACC RAM

read the LUT RAM

write the LUT RAM

hclr(1:0) Control the clearing of the ACC RAM during I/O mode

hclr0

hclr1

FUNCTION

0

0

1

1

0

1

0

1

ACC RAM cleared when either the ACC RAM or LUT RAM is

accessed

Undefined

ACC RAM cleared only when the ACC RAM is accessed

ACC RAM not cleared during an i/o operation

func

Determines the function performed by the marker processor. When high, each marker

circuit within the processor will locate an accumulated count from the ACC RAM

corresponding to the previously given grey value. When low, each marker will locate the

grey value corresponding to a previously given accumulation count from the ACC RAM.

pdwn When high, the ACC and LUT RAMs are placed in an inactive mode. Should be low for

normal operation.

Memory Configurations

The following memory maps specify the configuration of the ACC RAM and the LUT RAM in the

various computational modes.

ACC RAM Histogram Mode:

Grey Level

Memory Contents

0

Count for Grey Value 0

1

Count for Grey Value 1

.

.

.

.

.

.

.

.

511

Count for Grey Value 511