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N8044AH Datasheet(PDF) 4 Page - InnovASIC, Inc |
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N8044AH Datasheet(HTML) 4 Page - InnovASIC, Inc |
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4 / 65 page  IA8044/IA8344 Data Sheet SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 4 of 65 1-888-824-4184 ® 4.8.1 Accumulator (ACC)........................................................................................32 4.8.2 B Register (B) .................................................................................................32 4.8.3 Program Status Word (PSW)..........................................................................32 4.8.4 Stack Pointer (SP)...........................................................................................33 4.8.5 Data Pointer (DPTR) ......................................................................................33 4.9 Interrupts .....................................................................................................................34 4.9.1 External Interrupts ..........................................................................................34 4.9.2 Timer 0 and Timer 1 Interrupts ......................................................................34 4.9.3 Serial Interface Unit Interrupt.........................................................................34 4.9.4 Interrupt Priority Level Structure ...................................................................34 4.9.5 Interrupt Handling ..........................................................................................35 4.9.6 Interrupt Priority Register (IP)........................................................................35 4.9.7 Interrupt Enable Register (IE) ........................................................................36 4.10 SIU—Serial Interface Unit..........................................................................................36 4.10.1 SIU Special Function Registers ......................................................................37 4.10.2 Serial Mode Register (SMD) ..........................................................................37 4.10.3 Status/Command Register (STS) ....................................................................38 4.10.4 Send/Receive Count Register (NSNR) ...........................................................39 4.10.5 Station Address Register (STAD) ..................................................................40 4.10.6 Transmit Buffer Start Address Register (TBS) ..............................................40 4.10.7 Transmit Buffer Length Register (TBL).........................................................40 4.10.8 Transmit Control Byte Register (TCB) ..........................................................40 4.10.9 Receive Buffer Start Address Register (RBS)................................................41 4.10.10 Receive Buffer Length Register (RBL) ..........................................................41 4.10.11 Receive Field Length Register (RFL).............................................................41 4.10.12 Receive Control Byte Register (RCB)............................................................41 4.10.13 DMA Count Register (DMA CNT) ................................................................42 4.10.14 DMA Count Register (FIFO)..........................................................................42 4.10.15 SIU State Counter (SIUST) ............................................................................42 4.11 Data Clocking Options ................................................................................................43 4.12 Operational Modes ......................................................................................................43 4.13 Frame Format Options ................................................................................................44 4.14 HDLC Restrictions ......................................................................................................46 4.15 SIU Details ..................................................................................................................46 4.15.1 BIP ..................................................................................................................46 4.15.2 BYP.................................................................................................................48 4.16 Diagnostics ..................................................................................................................48 5. AC Specifications .................................................................................................................50 5.1 Memory Access Waveforms .......................................................................................51 5.2 Serial I/O Waveforms..................................................................................................55 |
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