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FIDO1100PQF208IR1 Datasheet(PDF) 10 Page - InnovASIC, Inc |
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FIDO1100PQF208IR1 Datasheet(HTML) 10 Page - InnovASIC, Inc |
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10 / 74 page  Flexible Input Deterministic Output (fido®) Data Sheet 32-Bit Real-Time Communications Controller April 10, 2013 IA211080807-10 http://www.innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 10 of 74 1-888-824-4184 JTAG emulation and debug interface Available in 208-pin PQFP and BGA 15- by 15-mm packages 3.3V operation with 5V-tolerant I/O Industrial temperature grade Software development supported by libraries and tools including UIC firmware for various interface protocols and formats, as well as a customized GNU tool set. 2.1 Core CPU The fido1100 core is based on the CPU32 architecture, and is compatible with the CPU32 instruction set. The fido1100 incorporates five independent hardware contexts. While all contexts share the same Execution Unit, each of the five hardware contexts in the fido1100 has its own register set, execution priority and exception vector table. From an application’s view, this unique feature of the fido1100 allows it to operate as five independent machines in one: 32-bit address and data paths on-chip 66-MHz operation Instruction execution from external memory or fast internal memory. Each hardware context has its own copy of: – Eight 32-bit User Data Registers (D0-D7) – Seven 32-bit Address Registers (A0-A6) – Two 32-bit Stack Pointers (A7 and A7') – One 32-bit Program Counter – One 16-bit Status Register (SR) – One 32-bit Vector Base Register (VBR) 2.2 JTAG The fido1100 is fully compliant with the IEEE 1149.1 Test Access Port and Boundary-Scan architecture (see Table 2). The fido1100 architecture is equipped with the TAP (Test Access Port) interface, TAP controller, instruction register, instruction decoder, boundary-scan register, and by-pass register. |
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