R1EX25008ASA00G/R1EX25008ATA00G/R1EX25016ASA00G/R1EX25016ATA00G

Preliminary

Functional Description

Status Register

The following figure shows the Status Register Format. The Status Register contains a number of status and control

bits that can be read or set (as appropriate) by specific instructions.

Status Register Format

SRWD

0

0

0

BP1

BP0

WEL

WIP

b7

Status Register Write Disable

Block Protect Bits

Write Enable Latch Bits

Write In Progress Bits

b0

WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register

cycle.

WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software

protected against Write instructions.

SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal.

The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.

Instructions

Each instruction starts with a single-byte code, as summarized in the following table. If an invalid instruction is sent

(one not contained in the following table), the device automatically deselects itself.

Instruction Set

Instruction

Description

Instruction Format

WREN

Write Enable

0000 0110

WRDI

Write Disable

0000 0100

RDSR

Read Status Register

0000 0101

WRSR

Write Status Register

0000 0001

READ

Read from Memory Array

0000 0011

WRITE

Write to Memory Array

0000 0010

R10DS0083EJ0100 Rev.1.00

Page 9 of 20

Oct. 02, 2012