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R1EX24512BTAS0IU0 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R1EX24512BTAS0IU0 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 19 page R1EX24512BSAS0I/R1EX24512BTAS0I R10DS0026EJ0400 Rev.4.00 Page 10 of 17 Sep, 20, 2013 Write Operations (WP=Low) Byte Write: (Write operation during WP=Low status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. Byte Write Operation Device address 1st Memory address (n) 2nd Memory address (n) Write data (n) 512k 10 10 W Stop Start ACK ACK ACK R/W WP ACK Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 128 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a6 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 128 bytes. If the a0 to a6 address bits reaches the last address of the page, the a0 to a6 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation Device address 1st Memory address (n) 2nd Memory address (n) Write data (n+m) Write data (n) 512k 10 10 W Stop Start ACK ACK ACK ACK ACK R/W WP |
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