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NDP4060L Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. NDP4060L
Description  N-Channel Logic Level Enhancement Mode Field Effect Transistor
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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NDP4060L Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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April 1996
NDP4060L / NDB4060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
________________________________________________________________________________
Absolute Maximum Ratings
T
C = 25°C unless otherwise noted
Symbol
Parameter
NDP4060L
NDB4060L
Units
V
DSS
Drain-Source Voltage
60
V
V
DGR
Drain-Gate Voltage (R
GS < 1 M)
60
V
V
GSS
Gate-Source Voltage - Continuous
± 16
V
- Nonrepetitive (t
P < 50 µs)
± 25
I
D
Drain Current
- Continuous
15
A
- Pulsed
45
P
D
Total Power Dissipation @ T
C = 25°C
50
W
Derate above 25°C
0.33
W/°C
T
J,TSTG
Operating and Storage Temperature
-65 to 175
°C
T
L
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
275
°C
NDP4060L Rev. B / NDB4060L Rev. C
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
15A, 60V. R
DS(ON) = 0.1@ VGS = 5V
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH) < 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON).
TO-220 and TO-263 (D
2PAK) package for both through hole
and surface mount applications.
S
D
G
© 1997 Fairchild Semiconductor Corporation


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