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S1C33L19 Datasheet(PDF) 1 Page - Epson Company |
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S1C33L19 Datasheet(HTML) 1 Page - Epson Company |
1 / 8 page S1C33L19 CMOS 32-bit Application Specific Controller ● 32-bit RISC CPU-Core Optimized for SoC (EPSON S1C33 PE) ● Dual AMBA Bus System for CPU and LCDC ● Built-in PLL (Multiplication rate: ×1 to ×16) ● Advanced CPU Instruction Queue Buffer ● Built-in 8KB RAM + Built-in VRAM/RAM (12KB) ● SDRAM Controller with Burst Control ● Generic DMA Controller (HSDMA/IDMA) ● 4-ch. PWM Control Timer/Counter ● Supports Several Interfaces SIO with FIFO (IrDA1.0, ISO7816-3), SPI, I2S and USB ● 5-ch. ADC for Analog Input ● Built-in LCD Controller with 12KB IVRAM Supports Up to QVGA (320 × 240) Display in 1 bpp Mode (black and white) by Single Chip Supports VGA (640 × 480) and 64K Color ● Built-in JPEG decoder/encoder ● Built-in USB controller (Device) Full speed (12Mbps) ● Supports I 2S interface (In/Out) ● NAND Flash Interface DESCRIPTIONS The S1C33L19 is a cost-effective, high-performance 32-bit RISC controller designed specifically for graphic display applications. It incorporates LCD display functions and JPEG image processing for electronic devices requiring LCD display of images, such as photo viewers and other compact image display units, home intercoms and other home electronic devices, as well as operating panels incorporated into various office equipment. The JPEG image processing function uses an internal hardware accelerator for high-load JPEG processing to achieve faster processing than software processing alone. It is provided as an easy-to-use JPEG decoder/encoder API with complex controls handled internally, allowing easy interfacing with applications for easy, high-speed enlargement and compression of JPEG image data, including photographs, improved application display capabilities, and smaller data sizes. Peripheral circuits and pin layout are completely forward-compatible with the S1C33L17, enabling use with applications that rely on ADC functions and a wide range of serial interfaces, including numerous general-purpose input/output ports, powerful PWM timer/counter, and USB-FS device controller. The S1C33L19 consists of a 32-bit RISC CPU core, JPEG decoder/encoder, general-purpose DMA controller, USB-FS device controller, PWM control timer/counter, several interfaces (IrDA1.0, SIO including ISO7816-3 protocol, SPI and I2S), ADC, RAM, general-purpose RAM shared IVRAM, RTC, and NAND Flash interface implemented by EPSON SoC design technology using a 0.18 μm fine-pattern CMOS process. FEATURES ● Technology ・ 0.18 μm AL-4-Layers mixed analog low power CMOS process technology ● CPU ・ EPSON original C33 PE 32-bit RISC CPU-Core with AMBA bus optimized for SoC ・ Max. 66 MHz operation ・ Internal 2-stage pipeline and 4 instruction queues ・ Instruction set: 128 instructions (16-bit fixed length) ・ Basic instructions are compatible with the S1C33 32-bit RISC Cores. ・ Dual AMBA bus system for CPU and LCDC |
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