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ADP1754ACPZ-1.5-R7 Datasheet(PDF) 12 Page - Analog Devices |
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ADP1754ACPZ-1.5-R7 Datasheet(HTML) 12 Page - Analog Devices |
12 / 20 page ADP1754/ADP1755 Data Sheet Rev. F | Page 12 of 20 CH1 2.0V BW CH2 500mV BW M40µs A CH1 920mV 1 2 T 9.8% T EN VOUT 500mV/DIV VOUT = 1.5V CIN = COUT = 4.7µF Figure 27. VOUT Ramp-Up with Internal Soft Start ADJUSTABLE OUTPUT VOLTAGE (ADP1755) The output voltage of the ADP1755 can be set over a 0.75 V to 3.3 V range. The output voltage is set by connecting a resistive voltage divider from VOUT to ADJ. The output voltage is calcu- lated using the following equation: VOUT = 0.5 V × (1 + R1/R2) (2) where: R1 is the resistor from VOUT to ADJ. R2 is the resistor from ADJ to GND. The maximum bias current into ADJ is 150 nA. Therefore, to achieve less than 0.5% error due to the bias current, use values less than 60 kΩ for R2. ENABLE FEATURE The ADP1754/ADP1755 use the EN pin to enable and disable the VOUT pins under normal operating conditions. As shown in Figure 28, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. 2 CH1 500mV BW CH2 500mV BW M2.0ms A CH1 1.05V 1 T 29.6% T EN VOUT 500mV/DIV VOUT = 1.5V CIN = COUT = 4.7µF Figure 28. Typical EN Pin Operation As shown in Figure 28, the EN pin has hysteresis built in. This hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 1.6 V to 3.6 V. 1.1 0.5 0.6 0.7 0.8 0.9 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 INPUT VOLTAGE (V) EN ACTIVE EN INACTIVE Figure 29. Typical EN Pin Thresholds vs. Input Voltage POWER-GOOD FEATURE The ADP1754/ADP1755 provide a power-good pin, PG, to indicate the status of the output. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal output voltage, PG imme- diately transitions low. During soft start, the rising threshold of the power-good signal is 93.5% of the nominal output voltage. The open-drain output is held low when the ADP1754/ADP1755 have sufficient input voltage to turn on the internal PG transistor. An optional soft start delay can be detected. The PG transistor is terminated via a pull-up resistor to VOUT or VIN. Power-good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger a power no-good if VOUT falls below 90%. A normal power-down triggers a power no-good when VOUT drops below 90%. |
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