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ADM1069ASTZ Datasheet(PDF) 8 Page - Analog Devices

Part No. ADM1069ASTZ
Description  Super Sequencer with Margining Control
Download  32 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM1069ASTZ Datasheet(HTML) 8 Page - Analog Devices

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ADM1069
Rev. C | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
24
25
32
8
9
17
16
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PIN 1
INDICATOR
ADM1069
TOP VIEW
(Not to Scale)
NC
VX1
VX2
VX3
VX4
NC
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
NC
NC
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
TOP VIEW
(Not to Scale)
ADM1069
2. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM.
THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS
PAD SHOULD BE SOLDERED TO THE BOARD FOR
IMPROVED MECHANICAL STABILITY.
Figure 3. LQFP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
LQFP
LFCSP1
Description
1, 6, 15,
16, 21,
22, 37, 38
NC
No Connect.
1 to 4
2 to 5
VX1 to VX4 (VXx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V
to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
5 to 7
7 to 9
VP1 to VP3 (VPx)
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and from 0.573 V
to 1.375 V.
8
10
VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
9
11
AGND2
Ground Return for Input Attenuators.
10
12
REFGND2
Ground Return for On-Chip Reference Circuits.
11
13
REFIN
Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage. The
on-board reference can be used by connecting the REFOUT pin to the REFIN pin. This is the normal
configuration.
12
14
REFOUT
2.048 V Reference Output. A reservoir capacitor must be connected between this pin and GND.
A 10 μF capacitor is recommended for this purpose.
13 to 16
17 to 20
DAC1 to DAC4
Voltage Output DACs. These pins default to high impedance at power-up.
17 to 24
23 to 30
PDO8 to PDO1
Programmable Output Drivers.
25
31
PDOGND2
Ground Return for Output Drivers.
26
32
VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this
pin and GND. A 10 μF capacitor is recommended for this purpose.
27
33
A0
Logic Input. This pin sets the seventh bit of the SMBus interface address.
28
34
A1
Logic Input. This pin sets the sixth bit of the SMBus interface address.
29
35
SCL
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
30
36
SDA
SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.


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