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PK60N512VMD100 Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc |
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PK60N512VMD100 Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 80 page  Table 5. Power mode transition operating behaviors Symbol Description Min. Max. Unit Notes tPOR After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VDD slew rate ≥ 5.7 kV/s • VDD slew rate < 5.7 kV/s — — 300 1.7 V / (VDD slew rate) μs 1 • VLLS1 → RUN — 130 μs • VLLS2 → RUN — 92 μs • VLLS3 → RUN — 92 μs • LLS → RUN — 5.9 μs • VLPS → RUN — 5.0 μs • STOP → RUN — 5.0 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description Min. Typ. Max. Unit Notes IDDA Analog supply current — — See note mA 1 IDD_RUN Run mode current — all peripheral clocks disabled, code executing from flash • @ 1.8V • @ 3.0V — — 37 38 63 64 mA mA 2 IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash • @ 1.8V • @ 3.0V • @ 25°C • @ 125°C — — — 46 47 58 77 63 79 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 20 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 9 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.12 — mA 6 Table continues on the next page... General K60 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 17 |
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