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PK60N512VMD100 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc |
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PK60N512VMD100 Datasheet(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 80 page  Table 4. Voltage and current operating behaviors (continued) Symbol Description Min. Typ.1 Max. Unit Notes IIND Input leakage current, digital pins • VDD < VIN < 5.5 V — 1 50 μA 4, 5 ZIND Input impedance examples, digital pins • VDD = 3.6 V • VDD = 3.0 V • VDD = 2.5 V • VDD = 1.7 V — — — — — — — — 48 55 57 85 kΩ kΩ kΩ kΩ 4, 7 RPU Internal pullup resistors 20 35 50 kΩ 8 RPD Internal pulldown resistors 20 35 50 kΩ 9 1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted. 2. Open drain outputs must be pulled to VDD. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. 5. Internal pull-up/pull-down resistors disabled. 6. Characterized, not tested in production. 7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. 8. Measured at VDD supply voltage = VDD min and Vinput = VSS 9. Measured at VDD supply voltage = VDD min and Vinput = VDD + – Digital input Source Z IND I IND 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • FlexBus clock = 50 MHz • Flash clock = 25 MHz • MCG mode: FEI General K60 Sub-Family Data Sheet, Rev. 3, 6/2013. 16 Freescale Semiconductor, Inc. |
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